Lines Matching refs:BaseReg
167 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
170 if ((BaseReg.getReg() != 0 &&
171 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
182 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
185 if ((BaseReg.getReg() != 0 &&
186 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
197 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
200 if ((BaseReg.getReg() != 0 &&
201 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
307 unsigned BaseReg = Base.getReg();
310 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
335 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
338 // If no BaseReg, issue a RIP relative instruction only if the MCE can
350 (!is64BitMode() || BaseReg != 0)) {
352 if (BaseReg == 0) { // [disp32] in X86-32 mode
387 if (BaseReg == 0) {
415 if (BaseReg == 0) {
