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      1 //===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This implements routines for translating functions from LLVM IR into
     11 // Machine IR.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
     16 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
     17 
     18 #include "llvm/ADT/APInt.h"
     19 #include "llvm/ADT/DenseMap.h"
     20 #include "llvm/ADT/IndexedMap.h"
     21 #include "llvm/ADT/SmallPtrSet.h"
     22 #include "llvm/ADT/SmallVector.h"
     23 #include "llvm/CodeGen/MachineBasicBlock.h"
     24 #include "llvm/CodeGen/ValueTypes.h"
     25 #include "llvm/IR/InlineAsm.h"
     26 #include "llvm/IR/Instructions.h"
     27 #include "llvm/Target/TargetRegisterInfo.h"
     28 #include <vector>
     29 
     30 namespace llvm {
     31 
     32 class AllocaInst;
     33 class BasicBlock;
     34 class BranchProbabilityInfo;
     35 class CallInst;
     36 class Function;
     37 class GlobalVariable;
     38 class Instruction;
     39 class MachineInstr;
     40 class MachineBasicBlock;
     41 class MachineFunction;
     42 class MachineModuleInfo;
     43 class MachineRegisterInfo;
     44 class TargetLowering;
     45 class Value;
     46 
     47 //===--------------------------------------------------------------------===//
     48 /// FunctionLoweringInfo - This contains information that is global to a
     49 /// function that is used when lowering a region of the function.
     50 ///
     51 class FunctionLoweringInfo {
     52 public:
     53   const TargetLowering &TLI;
     54   const Function *Fn;
     55   MachineFunction *MF;
     56   MachineRegisterInfo *RegInfo;
     57   BranchProbabilityInfo *BPI;
     58   /// CanLowerReturn - true iff the function's return value can be lowered to
     59   /// registers.
     60   bool CanLowerReturn;
     61 
     62   /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
     63   /// allocated to hold a pointer to the hidden sret parameter.
     64   unsigned DemoteRegister;
     65 
     66   /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
     67   DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
     68 
     69   /// ValueMap - Since we emit code for the function a basic block at a time,
     70   /// we must remember which virtual registers hold the values for
     71   /// cross-basic-block values.
     72   DenseMap<const Value*, unsigned> ValueMap;
     73 
     74   /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
     75   /// the entry block.  This allows the allocas to be efficiently referenced
     76   /// anywhere in the function.
     77   DenseMap<const AllocaInst*, int> StaticAllocaMap;
     78 
     79   /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
     80   DenseMap<const Argument*, int> ByValArgFrameIndexMap;
     81 
     82   /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
     83   /// function arguments that are inserted after scheduling is completed.
     84   SmallVector<MachineInstr*, 8> ArgDbgValues;
     85 
     86   /// RegFixups - Registers which need to be replaced after isel is done.
     87   DenseMap<unsigned, unsigned> RegFixups;
     88 
     89   /// MBB - The current block.
     90   MachineBasicBlock *MBB;
     91 
     92   /// MBB - The current insert position inside the current block.
     93   MachineBasicBlock::iterator InsertPt;
     94 
     95 #ifndef NDEBUG
     96   SmallPtrSet<const Instruction *, 8> CatchInfoLost;
     97   SmallPtrSet<const Instruction *, 8> CatchInfoFound;
     98 #endif
     99 
    100   struct LiveOutInfo {
    101     unsigned NumSignBits : 31;
    102     bool IsValid : 1;
    103     APInt KnownOne, KnownZero;
    104     LiveOutInfo() : NumSignBits(0), IsValid(true), KnownOne(1, 0),
    105                     KnownZero(1, 0) {}
    106   };
    107 
    108   /// VisitedBBs - The set of basic blocks visited thus far by instruction
    109   /// selection.
    110   SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
    111 
    112   /// PHINodesToUpdate - A list of phi instructions whose operand list will
    113   /// be updated after processing the current basic block.
    114   /// TODO: This isn't per-function state, it's per-basic-block state. But
    115   /// there's no other convenient place for it to live right now.
    116   std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
    117 
    118   explicit FunctionLoweringInfo(const TargetLowering &TLI);
    119 
    120   /// set - Initialize this FunctionLoweringInfo with the given Function
    121   /// and its associated MachineFunction.
    122   ///
    123   void set(const Function &Fn, MachineFunction &MF);
    124 
    125   /// clear - Clear out all the function-specific state. This returns this
    126   /// FunctionLoweringInfo to an empty state, ready to be used for a
    127   /// different function.
    128   void clear();
    129 
    130   /// isExportedInst - Return true if the specified value is an instruction
    131   /// exported from its block.
    132   bool isExportedInst(const Value *V) {
    133     return ValueMap.count(V);
    134   }
    135 
    136   unsigned CreateReg(MVT VT);
    137 
    138   unsigned CreateRegs(Type *Ty);
    139 
    140   unsigned InitializeRegForValue(const Value *V) {
    141     unsigned &R = ValueMap[V];
    142     assert(R == 0 && "Already initialized this value register!");
    143     return R = CreateRegs(V->getType());
    144   }
    145 
    146   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
    147   /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
    148   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
    149     if (!LiveOutRegInfo.inBounds(Reg))
    150       return NULL;
    151 
    152     const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
    153     if (!LOI->IsValid)
    154       return NULL;
    155 
    156     return LOI;
    157   }
    158 
    159   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
    160   /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
    161   /// the register's LiveOutInfo is for a smaller bit width, it is extended to
    162   /// the larger bit width by zero extension. The bit width must be no smaller
    163   /// than the LiveOutInfo's existing bit width.
    164   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
    165 
    166   /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
    167   void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
    168                          const APInt &KnownZero, const APInt &KnownOne) {
    169     // Only install this information if it tells us something.
    170     if (NumSignBits == 1 && KnownZero == 0 && KnownOne == 0)
    171       return;
    172 
    173     LiveOutRegInfo.grow(Reg);
    174     LiveOutInfo &LOI = LiveOutRegInfo[Reg];
    175     LOI.NumSignBits = NumSignBits;
    176     LOI.KnownOne = KnownOne;
    177     LOI.KnownZero = KnownZero;
    178   }
    179 
    180   /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
    181   /// register based on the LiveOutInfo of its operands.
    182   void ComputePHILiveOutRegInfo(const PHINode*);
    183 
    184   /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
    185   /// called when a block is visited before all of its predecessors.
    186   void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
    187     // PHIs with no uses have no ValueMap entry.
    188     DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
    189     if (It == ValueMap.end())
    190       return;
    191 
    192     unsigned Reg = It->second;
    193     LiveOutRegInfo.grow(Reg);
    194     LiveOutRegInfo[Reg].IsValid = false;
    195   }
    196 
    197   /// setArgumentFrameIndex - Record frame index for the byval
    198   /// argument.
    199   void setArgumentFrameIndex(const Argument *A, int FI);
    200 
    201   /// getArgumentFrameIndex - Get frame index for the byval argument.
    202   int getArgumentFrameIndex(const Argument *A);
    203 
    204 private:
    205   /// LiveOutRegInfo - Information about live out vregs.
    206   IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
    207 };
    208 
    209 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
    210 /// being passed to this variadic function, and set the MachineModuleInfo's
    211 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
    212 /// reference to _fltused on Windows, which will link in MSVCRT's
    213 /// floating-point support.
    214 void ComputeUsesVAFloatArgument(const CallInst &I, MachineModuleInfo *MMI);
    215 
    216 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
    217 /// call, and add them to the specified machine basic block.
    218 void AddCatchInfo(const CallInst &I,
    219                   MachineModuleInfo *MMI, MachineBasicBlock *MBB);
    220 
    221 /// AddLandingPadInfo - Extract the exception handling information from the
    222 /// landingpad instruction and add them to the specified machine module info.
    223 void AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
    224                        MachineBasicBlock *MBB);
    225 
    226 } // end namespace llvm
    227 
    228 #endif
    229