| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 77 int Opc = MI->getOpcode();
78 if (Opc == Hexagon::STriw_pred) {
122 } else if (Opc == Hexagon::LDriw_pred) {
|
| HexagonCFGOptimizer.cpp | 54 static bool IsConditionalBranch(int Opc) {
55 return (Opc == Hexagon::JMP_c) || (Opc == Hexagon::JMP_cNot)
56 || (Opc == Hexagon::JMP_cdnPt) || (Opc == Hexagon::JMP_cdnNotPt);
60 static bool IsUnconditionalJump(int Opc) {
61 return (Opc == Hexagon::JMP);
107 int Opc = MI->getOpcode();
108 if (IsConditionalBranch(Opc)) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.h | 20 unsigned Opc, ImmOpnd;
21 Inst(unsigned Opc, unsigned ImmOpnd);
|
| MipsInstrInfo.cpp | 77 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
80 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
86 Cond.push_back(MachineOperand::CreateImm(Opc));
107 unsigned Opc = Cond[0].getImm();
108 const MCInstrDesc &MCID = get(Opc);
132 // Floating point branches: 1 (opc)
133 // Int BranchZero: 2 (opc, reg)
134 // Int Branch: 3 (opc, reg0, reg1)
|
| Mips16ISelDAGToDAG.cpp | 40 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty,
43 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
248 unsigned Opc = InFlag.getOpcode(); (void)Opc;
249 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
250 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
| Mips16InstrInfo.cpp | 72 unsigned Opc = 0;
76 Opc = Mips::MoveR3216;
79 Opc = Mips::Move32R16;
82 Opc = Mips::Mfhi16, SrcReg = 0;
86 Opc = Mips::Mflo16, SrcReg = 0;
89 assert(Opc && "Cannot copy registers");
91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
108 unsigned Opc = 0;
110 Opc = Mips::SwRxSpImmX16;
111 assert(Opc && "Register class not handled!")
[all...] |
| MipsSEISelDAGToDAG.cpp | 182 MipsSEDAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty,
185 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
204 unsigned Opc = InFlag.getOpcode(); (void)Opc;
206 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
207 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
410 if (Inst->Opc == Mips::LUi64)
411 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd)
[all...] |
| MipsSEInstrInfo.cpp | 44 unsigned Opc = MI->getOpcode();
46 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
47 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
48 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
49 (Opc == Mips::LDC164_P8))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 107 unsigned Opc = MBBI->getOpcode();
108 switch (Opc) {
152 unsigned Opc;
154 Opc = getLEArOpcode(IsLP64);
156 Opc = isSub
171 Opc = isSub
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
209 unsigned Opc = PI->getOpcode()
[all...] |
| X86RegisterInfo.cpp | 466 unsigned Opc = MI.getOpcode();
467 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
53 switch (Opc) {
122 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ?
126 TII.get(Opc), GlobalBaseReg)
128 if (Opc == ARM::LDRcp)
|
| Thumb1RegisterInfo.cpp | 129 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
132 if (Opc != ARM::tADDhirr)
143 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
148 if (Opc == ARM::tADDrSPi) {
182 int Opc = 0;
190 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
203 Opc = ARM::tADDrSPi;
212 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
217 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8
[all...] |
| Thumb1FrameLowering.cpp | 69 unsigned Opc = Old->getOpcode();
70 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
73 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
|
| ARMBaseRegisterInfo.cpp | 473 unsigned Opc = MI->getOpcode();
474 switch (Opc) {
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 196 unsigned Opc = MBlaze::BRID;
198 Opc = (unsigned)Cond[0].getImm();
202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
|
| MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode();
102 if (Opc != ISD::Constant)
213 unsigned Opc = MBlaze::ADDIK;
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 92 unsigned Opc;
94 Opc = MSP430::MOV16rr;
96 Opc = MSP430::MOV8rr;
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
|
| MSP430FrameLowering.cpp | 142 unsigned Opc = PI->getOpcode();
143 if (Opc != MSP430::POP16r && !PI->isTerminator())
|
| MSP430ISelDAGToDAG.cpp | 364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
369 CurDAG->SelectNodeTo(Op, Opc,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64BranchFixupPass.cpp | 283 int Opc = I->getOpcode();
290 switch (Opc) {
|
| AArch64InstrInfo.cpp | 45 unsigned Opc = 0;
72 Opc = AArch64::ORRxxx_lsl;
76 Opc = AArch64::ORRwww_lsl;
113 BuildMI(MBB, I, DL, get(Opc), DestReg)
132 static bool isCondBranch(unsigned Opc) {
133 return Opc == AArch64::Bcc || Opc == AArch64::CBZw || Opc == AArch64::CBZx ||
134 Opc == AArch64::CBNZw || Opc == AArch64::CBNZx |
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 412 unsigned Opc;
414 Opc = PPC::OR;
416 Opc = PPC::OR8;
418 Opc = PPC::FMR;
420 Opc = PPC::MCRF;
422 Opc = PPC::VOR;
424 Opc = PPC::CROR;
428 const MCInstrDesc &MCID = get(Opc);
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 465 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
466 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
477 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
482 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
487 assert(!(ImmS == 31 && !SF && Opc != BFM)
489 assert(!(ImmS == 63 && SF && Opc != BFM)
493 if (Opc == SBFM && ImmR == 0) {
496 } else if (Opc == UBFM && ImmR == 0) {
500 if (Opc == UBFM) {
517 switch (Opc) {
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelDAGToDAG.cpp | 159 unsigned int Opc = N->getOpcode();
163 switch (Opc) {
|
