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    Searched defs:RegClass (Results 1 - 8 of 8) sorted by null

  /external/llvm/lib/Target/AArch64/
AArch64FrameLowering.h 31 const TargetRegisterClass *RegClass; // E.g. GPR64RegClass
  /external/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 46 OwningArrayPtr<RCInfo> RegClass;
70 const RCInfo &RCI = RegClass[RC->getID()];
  /external/llvm/lib/Target/R600/MCTargetDesc/
SIMCCodeEmitter.cpp 79 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
80 return (AMDGPU::SSrc_32RegClassID == RegClass) ||
81 (AMDGPU::SSrc_64RegClassID == RegClass) ||
82 (AMDGPU::VSrc_32RegClassID == RegClass) ||
83 (AMDGPU::VSrc_64RegClassID == RegClass);
  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 45 short RegClass = MCID.OpInfo[OpNum].RegClass;
47 return TRI->getPointerRegClass(MF, RegClass);
50 if (RegClass < 0)
54 return TRI->getRegClass(RegClass);
  /external/llvm/lib/Target/R600/
SIISelLowering.cpp 417 /// \brief Test if RegClass is one of the VSrc classes
418 static bool isVSrc(unsigned RegClass) {
419 return AMDGPU::VSrc_32RegClassID == RegClass ||
420 AMDGPU::VSrc_64RegClassID == RegClass;
423 /// \brief Test if RegClass is one of the SSrc classes
424 static bool isSSrc(unsigned RegClass) {
425 return AMDGPU::SSrc_32RegClassID == RegClass ||
426 AMDGPU::SSrc_64RegClassID == RegClass;
493 /// \brief Does "Op" fit into register class "RegClass" ?
495 unsigned RegClass) const
    [all...]
  /external/llvm/include/llvm/MC/
MCInstrDesc.h 59 /// RegClass - This specifies the register class enumeration of the operand
63 int16_t RegClass;
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp     [all...]
  /external/llvm/utils/TableGen/
CodeGenRegisters.cpp 739 // Verify that all altorder members are regclass members.
    [all...]

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