1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the subtarget options of a Target machine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H 16 17 #include "llvm/MC/MCSubtargetInfo.h" 18 #include "llvm/Support/CodeGen.h" 19 20 namespace llvm { 21 22 class MachineFunction; 23 class MachineInstr; 24 class SDep; 25 class SUnit; 26 class TargetRegisterClass; 27 class TargetSchedModel; 28 template <typename T> class SmallVectorImpl; 29 30 //===----------------------------------------------------------------------===// 31 /// 32 /// TargetSubtargetInfo - Generic base class for all target subtargets. All 33 /// Target-specific options that control code generation and printing should 34 /// be exposed through a TargetSubtargetInfo-derived class. 35 /// 36 class TargetSubtargetInfo : public MCSubtargetInfo { 37 TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 38 void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 39 protected: // Can only create subclasses... 40 TargetSubtargetInfo(); 41 public: 42 // AntiDepBreakMode - Type of anti-dependence breaking that should 43 // be performed before post-RA scheduling. 44 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 45 typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector; 46 47 virtual ~TargetSubtargetInfo(); 48 49 /// Resolve a SchedClass at runtime, where SchedClass identifies an 50 /// MCSchedClassDesc with the isVariant property. This may return the ID of 51 /// another variant SchedClass, but repeated invocation must quickly terminate 52 /// in a nonvariant SchedClass. 53 virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, 54 const TargetSchedModel* SchedModel) const { 55 return 0; 56 } 57 58 /// \brief True if the subtarget should run MachineScheduler after aggressive 59 /// coalescing. 60 /// 61 /// This currently replaces the SelectionDAG scheduler with the "source" order 62 /// scheduler. It does not yet disable the postRA scheduler. 63 virtual bool enableMachineScheduler() const; 64 65 // enablePostRAScheduler - If the target can benefit from post-regalloc 66 // scheduling and the specified optimization level meets the requirement 67 // return true to enable post-register-allocation scheduling. In 68 // CriticalPathRCs return any register classes that should only be broken 69 // if on the critical path. 70 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 71 AntiDepBreakMode& Mode, 72 RegClassVector& CriticalPathRCs) const; 73 // adjustSchedDependency - Perform target specific adjustments to 74 // the latency of a schedule dependency. 75 virtual void adjustSchedDependency(SUnit *def, SUnit *use, 76 SDep& dep) const { } 77 78 /// \brief Reset the features for the subtarget. 79 virtual void resetSubtargetFeatures(const MachineFunction *MF) { } 80 }; 81 82 } // End llvm namespace 83 84 #endif 85
