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      1 //===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines a wrapper around MCSchedModel that allows the interface to
     11 // benefit from information currently only available in TargetInstrInfo.
     12 // Ideally, the scheduling interface would be fully defined in the MC layer.
     13 //
     14 //===----------------------------------------------------------------------===//
     15 
     16 #ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
     17 #define LLVM_CODEGEN_TARGETSCHEDULE_H
     18 
     19 #include "llvm/ADT/SmallVector.h"
     20 #include "llvm/MC/MCInstrItineraries.h"
     21 #include "llvm/MC/MCSchedule.h"
     22 #include "llvm/Target/TargetSubtargetInfo.h"
     23 
     24 namespace llvm {
     25 
     26 class TargetRegisterInfo;
     27 class TargetSubtargetInfo;
     28 class TargetInstrInfo;
     29 class MachineInstr;
     30 
     31 /// Provide an instruction scheduling machine model to CodeGen passes.
     32 class TargetSchedModel {
     33   // For efficiency, hold a copy of the statically defined MCSchedModel for this
     34   // processor.
     35   MCSchedModel SchedModel;
     36   InstrItineraryData InstrItins;
     37   const TargetSubtargetInfo *STI;
     38   const TargetInstrInfo *TII;
     39 
     40   SmallVector<unsigned, 16> ResourceFactors;
     41   unsigned MicroOpFactor; // Multiply to normalize microops to resource units.
     42   unsigned ResourceLCM;   // Resource units per cycle. Latency normalization factor.
     43 public:
     44   TargetSchedModel(): STI(0), TII(0) {}
     45 
     46   /// \brief Initialize the machine model for instruction scheduling.
     47   ///
     48   /// The machine model API keeps a copy of the top-level MCSchedModel table
     49   /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
     50   /// dynamic properties.
     51   void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
     52             const TargetInstrInfo *tii);
     53 
     54   /// Return the MCSchedClassDesc for this instruction.
     55   const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
     56 
     57   /// \brief TargetInstrInfo getter.
     58   const TargetInstrInfo *getInstrInfo() const { return TII; }
     59 
     60   /// \brief Return true if this machine model includes an instruction-level
     61   /// scheduling model.
     62   ///
     63   /// This is more detailed than the course grain IssueWidth and default
     64   /// latency properties, but separate from the per-cycle itinerary data.
     65   bool hasInstrSchedModel() const;
     66 
     67   const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
     68 
     69   /// \brief Return true if this machine model includes cycle-to-cycle itinerary
     70   /// data.
     71   ///
     72   /// This models scheduling at each stage in the processor pipeline.
     73   bool hasInstrItineraries() const;
     74 
     75   const InstrItineraryData *getInstrItineraries() const {
     76     if (hasInstrItineraries())
     77       return &InstrItins;
     78     return 0;
     79   }
     80 
     81   /// \brief Identify the processor corresponding to the current subtarget.
     82   unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
     83 
     84   /// \brief Maximum number of micro-ops that may be scheduled per cycle.
     85   unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
     86 
     87   /// \brief Number of cycles the OOO processor is expected to hide.
     88   unsigned getILPWindow() const { return SchedModel.ILPWindow; }
     89 
     90   /// \brief Return the number of issue slots required for this MI.
     91   unsigned getNumMicroOps(const MachineInstr *MI,
     92                           const MCSchedClassDesc *SC = 0) const;
     93 
     94   /// \brief Get the number of kinds of resources for this target.
     95   unsigned getNumProcResourceKinds() const {
     96     return SchedModel.getNumProcResourceKinds();
     97   }
     98 
     99   /// \brief Get a processor resource by ID for convenience.
    100   const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
    101     return SchedModel.getProcResource(PIdx);
    102   }
    103 
    104   typedef const MCWriteProcResEntry *ProcResIter;
    105 
    106   // \brief Get an iterator into the processor resources consumed by this
    107   // scheduling class.
    108   ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
    109     // The subtarget holds a single resource table for all processors.
    110     return STI->getWriteProcResBegin(SC);
    111   }
    112   ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
    113     return STI->getWriteProcResEnd(SC);
    114   }
    115 
    116   /// \brief Multiply the number of units consumed for a resource by this factor
    117   /// to normalize it relative to other resources.
    118   unsigned getResourceFactor(unsigned ResIdx) const {
    119     return ResourceFactors[ResIdx];
    120   }
    121 
    122   /// \brief Multiply number of micro-ops by this factor to normalize it
    123   /// relative to other resources.
    124   unsigned getMicroOpFactor() const {
    125     return MicroOpFactor;
    126   }
    127 
    128   /// \brief Multiply cycle count by this factor to normalize it relative to
    129   /// other resources. This is the number of resource units per cycle.
    130   unsigned getLatencyFactor() const {
    131     return ResourceLCM;
    132   }
    133 
    134   /// \brief Compute operand latency based on the available machine model.
    135   ///
    136   /// Computes and return the latency of the given data dependent def and use
    137   /// when the operand indices are already known. UseMI may be NULL for an
    138   /// unknown user.
    139   ///
    140   /// FindMin may be set to get the minimum vs. expected latency. Minimum
    141   /// latency is used for scheduling groups, while expected latency is for
    142   /// instruction cost and critical path.
    143   unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
    144                                  const MachineInstr *UseMI, unsigned UseOperIdx,
    145                                  bool FindMin) const;
    146 
    147   /// \brief Compute the instruction latency based on the available machine
    148   /// model.
    149   ///
    150   /// Compute and return the expected latency of this instruction independent of
    151   /// a particular use. computeOperandLatency is the prefered API, but this is
    152   /// occasionally useful to help estimate instruction cost.
    153   unsigned computeInstrLatency(const MachineInstr *MI) const;
    154 
    155   /// \brief Output dependency latency of a pair of defs of the same register.
    156   ///
    157   /// This is typically one cycle.
    158   unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
    159                                 const MachineInstr *DepMI) const;
    160 
    161 private:
    162   /// getDefLatency is a helper for computeOperandLatency. Return the
    163   /// instruction's latency if operand lookup is not required.
    164   /// Otherwise return -1.
    165   int getDefLatency(const MachineInstr *DefMI, bool FindMin) const;
    166 };
    167 
    168 } // namespace llvm
    169 
    170 #endif
    171