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      1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the ScheduleDAGInstrs class, which implements
     11 // scheduling for a MachineInstr-based dependency graph.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
     16 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
     17 
     18 #include "llvm/ADT/SparseSet.h"
     19 #include "llvm/ADT/SparseMultiSet.h"
     20 #include "llvm/CodeGen/ScheduleDAG.h"
     21 #include "llvm/CodeGen/TargetSchedule.h"
     22 #include "llvm/Support/Compiler.h"
     23 #include "llvm/Target/TargetRegisterInfo.h"
     24 
     25 namespace llvm {
     26   class MachineFrameInfo;
     27   class MachineLoopInfo;
     28   class MachineDominatorTree;
     29   class LiveIntervals;
     30   class RegPressureTracker;
     31 
     32   /// An individual mapping from virtual register number to SUnit.
     33   struct VReg2SUnit {
     34     unsigned VirtReg;
     35     SUnit *SU;
     36 
     37     VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
     38 
     39     unsigned getSparseSetIndex() const {
     40       return TargetRegisterInfo::virtReg2Index(VirtReg);
     41     }
     42   };
     43 
     44   /// Record a physical register access.
     45   /// For non data-dependent uses, OpIdx == -1.
     46   struct PhysRegSUOper {
     47     SUnit *SU;
     48     int OpIdx;
     49     unsigned Reg;
     50 
     51     PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
     52 
     53     unsigned getSparseSetIndex() const { return Reg; }
     54   };
     55 
     56   /// Use a SparseMultiSet to track physical registers. Storage is only
     57   /// allocated once for the pass. It can be cleared in constant time and reused
     58   /// without any frees.
     59   typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t> Reg2SUnitsMap;
     60 
     61   /// Use SparseSet as a SparseMap by relying on the fact that it never
     62   /// compares ValueT's, only unsigned keys. This allows the set to be cleared
     63   /// between scheduling regions in constant time as long as ValueT does not
     64   /// require a destructor.
     65   typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
     66 
     67   /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
     68   /// MachineInstrs.
     69   class ScheduleDAGInstrs : public ScheduleDAG {
     70   protected:
     71     const MachineLoopInfo &MLI;
     72     const MachineDominatorTree &MDT;
     73     const MachineFrameInfo *MFI;
     74 
     75     /// Live Intervals provides reaching defs in preRA scheduling.
     76     LiveIntervals *LIS;
     77 
     78     /// TargetSchedModel provides an interface to the machine model.
     79     TargetSchedModel SchedModel;
     80 
     81     /// isPostRA flag indicates vregs cannot be present.
     82     bool IsPostRA;
     83 
     84     /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
     85     /// the def-side latency only.
     86     bool UnitLatencies;
     87 
     88     /// The standard DAG builder does not normally include terminators as DAG
     89     /// nodes because it does not create the necessary dependencies to prevent
     90     /// reordering. A specialized scheduler can overide
     91     /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
     92     /// it has taken responsibility for scheduling the terminator correctly.
     93     bool CanHandleTerminators;
     94 
     95     /// State specific to the current scheduling region.
     96     /// ------------------------------------------------
     97 
     98     /// The block in which to insert instructions
     99     MachineBasicBlock *BB;
    100 
    101     /// The beginning of the range to be scheduled.
    102     MachineBasicBlock::iterator RegionBegin;
    103 
    104     /// The end of the range to be scheduled.
    105     MachineBasicBlock::iterator RegionEnd;
    106 
    107     /// The index in BB of RegionEnd.
    108     unsigned EndIndex;
    109 
    110     /// After calling BuildSchedGraph, each machine instruction in the current
    111     /// scheduling region is mapped to an SUnit.
    112     DenseMap<MachineInstr*, SUnit*> MISUnitMap;
    113 
    114     /// State internal to DAG building.
    115     /// -------------------------------
    116 
    117     /// Defs, Uses - Remember where defs and uses of each register are as we
    118     /// iterate upward through the instructions. This is allocated here instead
    119     /// of inside BuildSchedGraph to avoid the need for it to be initialized and
    120     /// destructed for each block.
    121     Reg2SUnitsMap Defs;
    122     Reg2SUnitsMap Uses;
    123 
    124     /// Track the last instructon in this region defining each virtual register.
    125     VReg2SUnitMap VRegDefs;
    126 
    127     /// PendingLoads - Remember where unknown loads are after the most recent
    128     /// unknown store, as we iterate. As with Defs and Uses, this is here
    129     /// to minimize construction/destruction.
    130     std::vector<SUnit *> PendingLoads;
    131 
    132     /// DbgValues - Remember instruction that precedes DBG_VALUE.
    133     /// These are generated by buildSchedGraph but persist so they can be
    134     /// referenced when emitting the final schedule.
    135     typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
    136       DbgValueVector;
    137     DbgValueVector DbgValues;
    138     MachineInstr *FirstDbgValue;
    139 
    140   public:
    141     explicit ScheduleDAGInstrs(MachineFunction &mf,
    142                                const MachineLoopInfo &mli,
    143                                const MachineDominatorTree &mdt,
    144                                bool IsPostRAFlag,
    145                                LiveIntervals *LIS = 0);
    146 
    147     virtual ~ScheduleDAGInstrs() {}
    148 
    149     /// \brief Get the machine model for instruction scheduling.
    150     const TargetSchedModel *getSchedModel() const { return &SchedModel; }
    151 
    152     /// \brief Resolve and cache a resolved scheduling class for an SUnit.
    153     const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
    154       if (!SU->SchedClass)
    155         SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
    156       return SU->SchedClass;
    157     }
    158 
    159     /// begin - Return an iterator to the top of the current scheduling region.
    160     MachineBasicBlock::iterator begin() const { return RegionBegin; }
    161 
    162     /// end - Return an iterator to the bottom of the current scheduling region.
    163     MachineBasicBlock::iterator end() const { return RegionEnd; }
    164 
    165     /// newSUnit - Creates a new SUnit and return a ptr to it.
    166     SUnit *newSUnit(MachineInstr *MI);
    167 
    168     /// getSUnit - Return an existing SUnit for this MI, or NULL.
    169     SUnit *getSUnit(MachineInstr *MI) const;
    170 
    171     /// startBlock - Prepare to perform scheduling in the given block.
    172     virtual void startBlock(MachineBasicBlock *BB);
    173 
    174     /// finishBlock - Clean up after scheduling in the given block.
    175     virtual void finishBlock();
    176 
    177     /// Initialize the scheduler state for the next scheduling region.
    178     virtual void enterRegion(MachineBasicBlock *bb,
    179                              MachineBasicBlock::iterator begin,
    180                              MachineBasicBlock::iterator end,
    181                              unsigned endcount);
    182 
    183     /// Notify that the scheduler has finished scheduling the current region.
    184     virtual void exitRegion();
    185 
    186     /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
    187     /// input.
    188     void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0);
    189 
    190     /// addSchedBarrierDeps - Add dependencies from instructions in the current
    191     /// list of instructions being scheduled to scheduling barrier. We want to
    192     /// make sure instructions which define registers that are either used by
    193     /// the terminator or are live-out are properly scheduled. This is
    194     /// especially important when the definition latency of the return value(s)
    195     /// are too high to be hidden by the branch or when the liveout registers
    196     /// used by instructions in the fallthrough block.
    197     void addSchedBarrierDeps();
    198 
    199     /// schedule - Order nodes according to selected style, filling
    200     /// in the Sequence member.
    201     ///
    202     /// Typically, a scheduling algorithm will implement schedule() without
    203     /// overriding enterRegion() or exitRegion().
    204     virtual void schedule() = 0;
    205 
    206     /// finalizeSchedule - Allow targets to perform final scheduling actions at
    207     /// the level of the whole MachineFunction. By default does nothing.
    208     virtual void finalizeSchedule() {}
    209 
    210     virtual void dumpNode(const SUnit *SU) const;
    211 
    212     /// Return a label for a DAG node that points to an instruction.
    213     virtual std::string getGraphNodeLabel(const SUnit *SU) const;
    214 
    215     /// Return a label for the region of code covered by the DAG.
    216     virtual std::string getDAGName() const;
    217 
    218   protected:
    219     void initSUnits();
    220     void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
    221     void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
    222     void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
    223     void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
    224   };
    225 
    226   /// newSUnit - Creates a new SUnit and return a ptr to it.
    227   inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
    228 #ifndef NDEBUG
    229     const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
    230 #endif
    231     SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
    232     assert((Addr == 0 || Addr == &SUnits[0]) &&
    233            "SUnits std::vector reallocated on the fly!");
    234     SUnits.back().OrigNode = &SUnits.back();
    235     return &SUnits.back();
    236   }
    237 
    238   /// getSUnit - Return an existing SUnit for this MI, or NULL.
    239   inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
    240     DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
    241     if (I == MISUnitMap.end())
    242       return 0;
    243     return I->second;
    244   }
    245 } // namespace llvm
    246 
    247 #endif
    248