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Searched
defs:Registers
(Results
1 - 9
of
9
) sorted by null
/external/v8/src/mips/
constants-mips.h
83
//
Registers
and FPURegisters.
85
// Number of general purpose
registers
.
89
// Number of
registers
with HI, LO, and pc.
95
// Number coprocessor
registers
.
99
// FPU (coprocessor 1) control
registers
. Currently only FCSR is implemented.
127
class
Registers
{
183
// the simulator will run through them and print the
registers
.
566
//
registers
and other constants.
/external/llvm/utils/TableGen/
RegisterInfoEmitter.cpp
38
// runEnums - Print out enum values for all of the
registers
.
70
// runEnums - Print out enum values for all of the
registers
.
73
const std::vector<CodeGenRegister*> &
Registers
= Bank.getRegisters();
76
assert(
Registers
.size() <= 0xffff && "Too many regs to fit in tables");
78
std::string Namespace =
Registers
[0]->TheDef->getValueAsString("Namespace");
95
for (unsigned i = 0, e =
Registers
.size(); i != e; ++i)
96
OS << " " <<
Registers
[i]->getName() << " = " <<
97
Registers
[i]->EnumValue << ",\n";
98
assert(
Registers
.size() ==
Registers
[Registers.size()-1]->EnumValue &
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CodeGenRegisters.h
113
// Lazily compute a map of all sub-
registers
.
114
// This includes unique entries for all sub-sub-
registers
.
117
// Compute extra sub-
registers
by combining the existing sub-
registers
.
120
// Add this as a super-register to all sub-
registers
after the sub-register
125
assert(SubRegsComplete && "Must precompute sub-
registers
");
129
// Add sub-
registers
to OSet following a pre-order defined by the .td file.
141
// Get the list of super-
registers
in topological order, small to large.
142
// This is valid after computeSubRegs visits all
registers
during RegBank
145
assert(SubRegsComplete && "Must precompute sub-
registers
");
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AsmMatcherEmitter.cpp
186
/// For register classes, the records for all the
registers
in this class.
187
std::set<Record*>
Registers
;
209
//
Registers
classes are only related to
registers
classes, and only if
217
std::set_intersection(
Registers
.begin(),
Registers
.end(),
218
RHS.
Registers
.begin(), RHS.
Registers
.end(),
775
// Collect singleton
registers
, if used.
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CodeGenRegisters.cpp
124
// Also compute leading super-
registers
. Each register has a list of
125
// covered-by-subregs super-
registers
where it appears as the first explicit
133
//
registers
, so build a symmetric graph by adding links in both ends.
147
// Iterate over all register units in a set of
registers
.
230
// Map explicit sub-
registers
first, so the names take precedence.
231
// The inherited sub-
registers
are mapped below.
330
// sub-
registers
. By doing this before computeSecondarySubRegs(), we ensure
351
// sub-
registers
, the other
registers
won't contribute any more units.
354
// Explicit sub-
registers
are usually disjoint, so this is a good way o
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/external/grub/netboot/
3c90x.c
54
enum
Registers
83
/** following are windowed
registers
**/
771
/** Program the MAC address into the station address
registers
**/
/external/v8/src/arm/
constants-arm.h
94
// Number of
registers
in normal ARM mode.
441
// These constants are declared in assembler-arm.cc, as they use named
registers
738
class
Registers
{
/external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp
52
// Map of register aliases
registers
via the .req directive.
317
SmallVector<unsigned, 8>
Registers
;
356
// A vector register list is a sequential list of 1 to 4
registers
.
465
Registers
= o.
Registers
;
549
return
Registers
;
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/external/robolectric/lib/main/
sqlite-jdbc-3.7.2.jar
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