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      1 //===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 /// \file
      9 //===----------------------------------------------------------------------===//
     10 
     11 #ifndef R600DEFINES_H_
     12 #define R600DEFINES_H_
     13 
     14 #include "llvm/MC/MCRegisterInfo.h"
     15 
     16 // Operand Flags
     17 #define MO_FLAG_CLAMP (1 << 0)
     18 #define MO_FLAG_NEG   (1 << 1)
     19 #define MO_FLAG_ABS   (1 << 2)
     20 #define MO_FLAG_MASK  (1 << 3)
     21 #define MO_FLAG_PUSH  (1 << 4)
     22 #define MO_FLAG_NOT_LAST  (1 << 5)
     23 #define MO_FLAG_LAST  (1 << 6)
     24 #define NUM_MO_FLAGS 7
     25 
     26 /// \brief Helper for getting the operand index for the instruction flags
     27 /// operand.
     28 #define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
     29 
     30 namespace R600_InstFlag {
     31   enum TIF {
     32     TRANS_ONLY = (1 << 0),
     33     TEX = (1 << 1),
     34     REDUCTION = (1 << 2),
     35     FC = (1 << 3),
     36     TRIG = (1 << 4),
     37     OP3 = (1 << 5),
     38     VECTOR = (1 << 6),
     39     //FlagOperand bits 7, 8
     40     NATIVE_OPERANDS = (1 << 9),
     41     OP1 = (1 << 10),
     42     OP2 = (1 << 11)
     43   };
     44 }
     45 
     46 #define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
     47 
     48 /// \brief Defines for extracting register infomation from register encoding
     49 #define HW_REG_MASK 0x1ff
     50 #define HW_CHAN_SHIFT 9
     51 
     52 #define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
     53 #define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
     54 
     55 namespace R600Operands {
     56   enum Ops {
     57     DST,
     58     UPDATE_EXEC_MASK,
     59     UPDATE_PREDICATE,
     60     WRITE,
     61     OMOD,
     62     DST_REL,
     63     CLAMP,
     64     SRC0,
     65     SRC0_NEG,
     66     SRC0_REL,
     67     SRC0_ABS,
     68     SRC0_SEL,
     69     SRC1,
     70     SRC1_NEG,
     71     SRC1_REL,
     72     SRC1_ABS,
     73     SRC1_SEL,
     74     SRC2,
     75     SRC2_NEG,
     76     SRC2_REL,
     77     SRC2_SEL,
     78     LAST,
     79     PRED_SEL,
     80     IMM,
     81     COUNT
     82  };
     83 
     84   const static int ALUOpTable[3][R600Operands::COUNT] = {
     85 //            W        C     S  S  S  S     S  S  S  S     S  S  S
     86 //            R  O  D  L  S  R  R  R  R  S  R  R  R  R  S  R  R  R  L  P
     87 //   D  U     I  M  R  A  R  C  C  C  C  R  C  C  C  C  R  C  C  C  A  R  I
     88 //   S  E  U  T  O  E  M  C  0  0  0  0  C  1  1  1  1  C  2  2  2  S  E  M
     89 //   T  M  P  E  D  L  P  0  N  R  A  S  1  N  R  A  S  2  N  R  S  T  D  M
     90     {0,-1,-1, 1, 2, 3, 4, 5, 6, 7, 8, 9,-1,-1,-1,-1,-1,-1,-1,-1,-1,10,11,12},
     91     {0, 1, 2, 3, 4 ,5 ,6 ,7, 8, 9,10,11,12,13,14,15,16,-1,-1,-1,-1,17,18,19},
     92     {0,-1,-1,-1,-1, 1, 2, 3, 4, 5,-1, 6, 7, 8, 9,-1,10,11,12,13,14,15,16,17}
     93   };
     94 
     95 }
     96 
     97 #endif // R600DEFINES_H_
     98