1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides basic encoding and assembly information for AArch64. 11 // 12 //===----------------------------------------------------------------------===// 13 #include "AArch64BaseInfo.h" 14 #include "llvm/ADT/APFloat.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/Support/Regex.h" 18 19 using namespace llvm; 20 21 StringRef NamedImmMapper::toString(uint32_t Value, bool &Valid) const { 22 for (unsigned i = 0; i < NumPairs; ++i) { 23 if (Pairs[i].Value == Value) { 24 Valid = true; 25 return Pairs[i].Name; 26 } 27 } 28 29 Valid = false; 30 return StringRef(); 31 } 32 33 uint32_t NamedImmMapper::fromString(StringRef Name, bool &Valid) const { 34 std::string LowerCaseName = Name.lower(); 35 for (unsigned i = 0; i < NumPairs; ++i) { 36 if (Pairs[i].Name == LowerCaseName) { 37 Valid = true; 38 return Pairs[i].Value; 39 } 40 } 41 42 Valid = false; 43 return -1; 44 } 45 46 bool NamedImmMapper::validImm(uint32_t Value) const { 47 return Value < TooBigImm; 48 } 49 50 const NamedImmMapper::Mapping A64AT::ATMapper::ATPairs[] = { 51 {"s1e1r", S1E1R}, 52 {"s1e2r", S1E2R}, 53 {"s1e3r", S1E3R}, 54 {"s1e1w", S1E1W}, 55 {"s1e2w", S1E2W}, 56 {"s1e3w", S1E3W}, 57 {"s1e0r", S1E0R}, 58 {"s1e0w", S1E0W}, 59 {"s12e1r", S12E1R}, 60 {"s12e1w", S12E1W}, 61 {"s12e0r", S12E0R}, 62 {"s12e0w", S12E0W}, 63 }; 64 65 A64AT::ATMapper::ATMapper() 66 : NamedImmMapper(ATPairs, 0) {} 67 68 const NamedImmMapper::Mapping A64DB::DBarrierMapper::DBarrierPairs[] = { 69 {"oshld", OSHLD}, 70 {"oshst", OSHST}, 71 {"osh", OSH}, 72 {"nshld", NSHLD}, 73 {"nshst", NSHST}, 74 {"nsh", NSH}, 75 {"ishld", ISHLD}, 76 {"ishst", ISHST}, 77 {"ish", ISH}, 78 {"ld", LD}, 79 {"st", ST}, 80 {"sy", SY} 81 }; 82 83 A64DB::DBarrierMapper::DBarrierMapper() 84 : NamedImmMapper(DBarrierPairs, 16u) {} 85 86 const NamedImmMapper::Mapping A64DC::DCMapper::DCPairs[] = { 87 {"zva", ZVA}, 88 {"ivac", IVAC}, 89 {"isw", ISW}, 90 {"cvac", CVAC}, 91 {"csw", CSW}, 92 {"cvau", CVAU}, 93 {"civac", CIVAC}, 94 {"cisw", CISW} 95 }; 96 97 A64DC::DCMapper::DCMapper() 98 : NamedImmMapper(DCPairs, 0) {} 99 100 const NamedImmMapper::Mapping A64IC::ICMapper::ICPairs[] = { 101 {"ialluis", IALLUIS}, 102 {"iallu", IALLU}, 103 {"ivau", IVAU} 104 }; 105 106 A64IC::ICMapper::ICMapper() 107 : NamedImmMapper(ICPairs, 0) {} 108 109 const NamedImmMapper::Mapping A64ISB::ISBMapper::ISBPairs[] = { 110 {"sy", SY}, 111 }; 112 113 A64ISB::ISBMapper::ISBMapper() 114 : NamedImmMapper(ISBPairs, 16) {} 115 116 const NamedImmMapper::Mapping A64PRFM::PRFMMapper::PRFMPairs[] = { 117 {"pldl1keep", PLDL1KEEP}, 118 {"pldl1strm", PLDL1STRM}, 119 {"pldl2keep", PLDL2KEEP}, 120 {"pldl2strm", PLDL2STRM}, 121 {"pldl3keep", PLDL3KEEP}, 122 {"pldl3strm", PLDL3STRM}, 123 {"plil1keep", PLIL1KEEP}, 124 {"plil1strm", PLIL1STRM}, 125 {"plil2keep", PLIL2KEEP}, 126 {"plil2strm", PLIL2STRM}, 127 {"plil3keep", PLIL3KEEP}, 128 {"plil3strm", PLIL3STRM}, 129 {"pstl1keep", PSTL1KEEP}, 130 {"pstl1strm", PSTL1STRM}, 131 {"pstl2keep", PSTL2KEEP}, 132 {"pstl2strm", PSTL2STRM}, 133 {"pstl3keep", PSTL3KEEP}, 134 {"pstl3strm", PSTL3STRM} 135 }; 136 137 A64PRFM::PRFMMapper::PRFMMapper() 138 : NamedImmMapper(PRFMPairs, 32) {} 139 140 const NamedImmMapper::Mapping A64PState::PStateMapper::PStatePairs[] = { 141 {"spsel", SPSel}, 142 {"daifset", DAIFSet}, 143 {"daifclr", DAIFClr} 144 }; 145 146 A64PState::PStateMapper::PStateMapper() 147 : NamedImmMapper(PStatePairs, 0) {} 148 149 const NamedImmMapper::Mapping A64SysReg::MRSMapper::MRSPairs[] = { 150 {"mdccsr_el0", MDCCSR_EL0}, 151 {"dbgdtrrx_el0", DBGDTRRX_EL0}, 152 {"mdrar_el1", MDRAR_EL1}, 153 {"oslsr_el1", OSLSR_EL1}, 154 {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1}, 155 {"pmceid0_el0", PMCEID0_EL0}, 156 {"pmceid1_el0", PMCEID1_EL0}, 157 {"midr_el1", MIDR_EL1}, 158 {"ccsidr_el1", CCSIDR_EL1}, 159 {"clidr_el1", CLIDR_EL1}, 160 {"ctr_el0", CTR_EL0}, 161 {"mpidr_el1", MPIDR_EL1}, 162 {"revidr_el1", REVIDR_EL1}, 163 {"aidr_el1", AIDR_EL1}, 164 {"dczid_el0", DCZID_EL0}, 165 {"id_pfr0_el1", ID_PFR0_EL1}, 166 {"id_pfr1_el1", ID_PFR1_EL1}, 167 {"id_dfr0_el1", ID_DFR0_EL1}, 168 {"id_afr0_el1", ID_AFR0_EL1}, 169 {"id_mmfr0_el1", ID_MMFR0_EL1}, 170 {"id_mmfr1_el1", ID_MMFR1_EL1}, 171 {"id_mmfr2_el1", ID_MMFR2_EL1}, 172 {"id_mmfr3_el1", ID_MMFR3_EL1}, 173 {"id_isar0_el1", ID_ISAR0_EL1}, 174 {"id_isar1_el1", ID_ISAR1_EL1}, 175 {"id_isar2_el1", ID_ISAR2_EL1}, 176 {"id_isar3_el1", ID_ISAR3_EL1}, 177 {"id_isar4_el1", ID_ISAR4_EL1}, 178 {"id_isar5_el1", ID_ISAR5_EL1}, 179 {"id_aa64pfr0_el1", ID_AA64PFR0_EL1}, 180 {"id_aa64pfr1_el1", ID_AA64PFR1_EL1}, 181 {"id_aa64dfr0_el1", ID_AA64DFR0_EL1}, 182 {"id_aa64dfr1_el1", ID_AA64DFR1_EL1}, 183 {"id_aa64afr0_el1", ID_AA64AFR0_EL1}, 184 {"id_aa64afr1_el1", ID_AA64AFR1_EL1}, 185 {"id_aa64isar0_el1", ID_AA64ISAR0_EL1}, 186 {"id_aa64isar1_el1", ID_AA64ISAR1_EL1}, 187 {"id_aa64mmfr0_el1", ID_AA64MMFR0_EL1}, 188 {"id_aa64mmfr1_el1", ID_AA64MMFR1_EL1}, 189 {"mvfr0_el1", MVFR0_EL1}, 190 {"mvfr1_el1", MVFR1_EL1}, 191 {"mvfr2_el1", MVFR2_EL1}, 192 {"rvbar_el1", RVBAR_EL1}, 193 {"rvbar_el2", RVBAR_EL2}, 194 {"rvbar_el3", RVBAR_EL3}, 195 {"isr_el1", ISR_EL1}, 196 {"cntpct_el0", CNTPCT_EL0}, 197 {"cntvct_el0", CNTVCT_EL0} 198 }; 199 200 A64SysReg::MRSMapper::MRSMapper() { 201 InstPairs = &MRSPairs[0]; 202 NumInstPairs = llvm::array_lengthof(MRSPairs); 203 } 204 205 const NamedImmMapper::Mapping A64SysReg::MSRMapper::MSRPairs[] = { 206 {"dbgdtrtx_el0", DBGDTRTX_EL0}, 207 {"oslar_el1", OSLAR_EL1}, 208 {"pmswinc_el0", PMSWINC_EL0} 209 }; 210 211 A64SysReg::MSRMapper::MSRMapper() { 212 InstPairs = &MSRPairs[0]; 213 NumInstPairs = llvm::array_lengthof(MSRPairs); 214 } 215 216 217 const NamedImmMapper::Mapping A64SysReg::SysRegMapper::SysRegPairs[] = { 218 {"osdtrrx_el1", OSDTRRX_EL1}, 219 {"osdtrtx_el1", OSDTRTX_EL1}, 220 {"teecr32_el1", TEECR32_EL1}, 221 {"mdccint_el1", MDCCINT_EL1}, 222 {"mdscr_el1", MDSCR_EL1}, 223 {"dbgdtr_el0", DBGDTR_EL0}, 224 {"oseccr_el1", OSECCR_EL1}, 225 {"dbgvcr32_el2", DBGVCR32_EL2}, 226 {"dbgbvr0_el1", DBGBVR0_EL1}, 227 {"dbgbvr1_el1", DBGBVR1_EL1}, 228 {"dbgbvr2_el1", DBGBVR2_EL1}, 229 {"dbgbvr3_el1", DBGBVR3_EL1}, 230 {"dbgbvr4_el1", DBGBVR4_EL1}, 231 {"dbgbvr5_el1", DBGBVR5_EL1}, 232 {"dbgbvr6_el1", DBGBVR6_EL1}, 233 {"dbgbvr7_el1", DBGBVR7_EL1}, 234 {"dbgbvr8_el1", DBGBVR8_EL1}, 235 {"dbgbvr9_el1", DBGBVR9_EL1}, 236 {"dbgbvr10_el1", DBGBVR10_EL1}, 237 {"dbgbvr11_el1", DBGBVR11_EL1}, 238 {"dbgbvr12_el1", DBGBVR12_EL1}, 239 {"dbgbvr13_el1", DBGBVR13_EL1}, 240 {"dbgbvr14_el1", DBGBVR14_EL1}, 241 {"dbgbvr15_el1", DBGBVR15_EL1}, 242 {"dbgbcr0_el1", DBGBCR0_EL1}, 243 {"dbgbcr1_el1", DBGBCR1_EL1}, 244 {"dbgbcr2_el1", DBGBCR2_EL1}, 245 {"dbgbcr3_el1", DBGBCR3_EL1}, 246 {"dbgbcr4_el1", DBGBCR4_EL1}, 247 {"dbgbcr5_el1", DBGBCR5_EL1}, 248 {"dbgbcr6_el1", DBGBCR6_EL1}, 249 {"dbgbcr7_el1", DBGBCR7_EL1}, 250 {"dbgbcr8_el1", DBGBCR8_EL1}, 251 {"dbgbcr9_el1", DBGBCR9_EL1}, 252 {"dbgbcr10_el1", DBGBCR10_EL1}, 253 {"dbgbcr11_el1", DBGBCR11_EL1}, 254 {"dbgbcr12_el1", DBGBCR12_EL1}, 255 {"dbgbcr13_el1", DBGBCR13_EL1}, 256 {"dbgbcr14_el1", DBGBCR14_EL1}, 257 {"dbgbcr15_el1", DBGBCR15_EL1}, 258 {"dbgwvr0_el1", DBGWVR0_EL1}, 259 {"dbgwvr1_el1", DBGWVR1_EL1}, 260 {"dbgwvr2_el1", DBGWVR2_EL1}, 261 {"dbgwvr3_el1", DBGWVR3_EL1}, 262 {"dbgwvr4_el1", DBGWVR4_EL1}, 263 {"dbgwvr5_el1", DBGWVR5_EL1}, 264 {"dbgwvr6_el1", DBGWVR6_EL1}, 265 {"dbgwvr7_el1", DBGWVR7_EL1}, 266 {"dbgwvr8_el1", DBGWVR8_EL1}, 267 {"dbgwvr9_el1", DBGWVR9_EL1}, 268 {"dbgwvr10_el1", DBGWVR10_EL1}, 269 {"dbgwvr11_el1", DBGWVR11_EL1}, 270 {"dbgwvr12_el1", DBGWVR12_EL1}, 271 {"dbgwvr13_el1", DBGWVR13_EL1}, 272 {"dbgwvr14_el1", DBGWVR14_EL1}, 273 {"dbgwvr15_el1", DBGWVR15_EL1}, 274 {"dbgwcr0_el1", DBGWCR0_EL1}, 275 {"dbgwcr1_el1", DBGWCR1_EL1}, 276 {"dbgwcr2_el1", DBGWCR2_EL1}, 277 {"dbgwcr3_el1", DBGWCR3_EL1}, 278 {"dbgwcr4_el1", DBGWCR4_EL1}, 279 {"dbgwcr5_el1", DBGWCR5_EL1}, 280 {"dbgwcr6_el1", DBGWCR6_EL1}, 281 {"dbgwcr7_el1", DBGWCR7_EL1}, 282 {"dbgwcr8_el1", DBGWCR8_EL1}, 283 {"dbgwcr9_el1", DBGWCR9_EL1}, 284 {"dbgwcr10_el1", DBGWCR10_EL1}, 285 {"dbgwcr11_el1", DBGWCR11_EL1}, 286 {"dbgwcr12_el1", DBGWCR12_EL1}, 287 {"dbgwcr13_el1", DBGWCR13_EL1}, 288 {"dbgwcr14_el1", DBGWCR14_EL1}, 289 {"dbgwcr15_el1", DBGWCR15_EL1}, 290 {"teehbr32_el1", TEEHBR32_EL1}, 291 {"osdlr_el1", OSDLR_EL1}, 292 {"dbgprcr_el1", DBGPRCR_EL1}, 293 {"dbgclaimset_el1", DBGCLAIMSET_EL1}, 294 {"dbgclaimclr_el1", DBGCLAIMCLR_EL1}, 295 {"csselr_el1", CSSELR_EL1}, 296 {"vpidr_el2", VPIDR_EL2}, 297 {"vmpidr_el2", VMPIDR_EL2}, 298 {"sctlr_el1", SCTLR_EL1}, 299 {"sctlr_el2", SCTLR_EL2}, 300 {"sctlr_el3", SCTLR_EL3}, 301 {"actlr_el1", ACTLR_EL1}, 302 {"actlr_el2", ACTLR_EL2}, 303 {"actlr_el3", ACTLR_EL3}, 304 {"cpacr_el1", CPACR_EL1}, 305 {"hcr_el2", HCR_EL2}, 306 {"scr_el3", SCR_EL3}, 307 {"mdcr_el2", MDCR_EL2}, 308 {"sder32_el3", SDER32_EL3}, 309 {"cptr_el2", CPTR_EL2}, 310 {"cptr_el3", CPTR_EL3}, 311 {"hstr_el2", HSTR_EL2}, 312 {"hacr_el2", HACR_EL2}, 313 {"mdcr_el3", MDCR_EL3}, 314 {"ttbr0_el1", TTBR0_EL1}, 315 {"ttbr0_el2", TTBR0_EL2}, 316 {"ttbr0_el3", TTBR0_EL3}, 317 {"ttbr1_el1", TTBR1_EL1}, 318 {"tcr_el1", TCR_EL1}, 319 {"tcr_el2", TCR_EL2}, 320 {"tcr_el3", TCR_EL3}, 321 {"vttbr_el2", VTTBR_EL2}, 322 {"vtcr_el2", VTCR_EL2}, 323 {"dacr32_el2", DACR32_EL2}, 324 {"spsr_el1", SPSR_EL1}, 325 {"spsr_el2", SPSR_EL2}, 326 {"spsr_el3", SPSR_EL3}, 327 {"elr_el1", ELR_EL1}, 328 {"elr_el2", ELR_EL2}, 329 {"elr_el3", ELR_EL3}, 330 {"sp_el0", SP_EL0}, 331 {"sp_el1", SP_EL1}, 332 {"sp_el2", SP_EL2}, 333 {"spsel", SPSel}, 334 {"nzcv", NZCV}, 335 {"daif", DAIF}, 336 {"currentel", CurrentEL}, 337 {"spsr_irq", SPSR_irq}, 338 {"spsr_abt", SPSR_abt}, 339 {"spsr_und", SPSR_und}, 340 {"spsr_fiq", SPSR_fiq}, 341 {"fpcr", FPCR}, 342 {"fpsr", FPSR}, 343 {"dspsr_el0", DSPSR_EL0}, 344 {"dlr_el0", DLR_EL0}, 345 {"ifsr32_el2", IFSR32_EL2}, 346 {"afsr0_el1", AFSR0_EL1}, 347 {"afsr0_el2", AFSR0_EL2}, 348 {"afsr0_el3", AFSR0_EL3}, 349 {"afsr1_el1", AFSR1_EL1}, 350 {"afsr1_el2", AFSR1_EL2}, 351 {"afsr1_el3", AFSR1_EL3}, 352 {"esr_el1", ESR_EL1}, 353 {"esr_el2", ESR_EL2}, 354 {"esr_el3", ESR_EL3}, 355 {"fpexc32_el2", FPEXC32_EL2}, 356 {"far_el1", FAR_EL1}, 357 {"far_el2", FAR_EL2}, 358 {"far_el3", FAR_EL3}, 359 {"hpfar_el2", HPFAR_EL2}, 360 {"par_el1", PAR_EL1}, 361 {"pmcr_el0", PMCR_EL0}, 362 {"pmcntenset_el0", PMCNTENSET_EL0}, 363 {"pmcntenclr_el0", PMCNTENCLR_EL0}, 364 {"pmovsclr_el0", PMOVSCLR_EL0}, 365 {"pmselr_el0", PMSELR_EL0}, 366 {"pmccntr_el0", PMCCNTR_EL0}, 367 {"pmxevtyper_el0", PMXEVTYPER_EL0}, 368 {"pmxevcntr_el0", PMXEVCNTR_EL0}, 369 {"pmuserenr_el0", PMUSERENR_EL0}, 370 {"pmintenset_el1", PMINTENSET_EL1}, 371 {"pmintenclr_el1", PMINTENCLR_EL1}, 372 {"pmovsset_el0", PMOVSSET_EL0}, 373 {"mair_el1", MAIR_EL1}, 374 {"mair_el2", MAIR_EL2}, 375 {"mair_el3", MAIR_EL3}, 376 {"amair_el1", AMAIR_EL1}, 377 {"amair_el2", AMAIR_EL2}, 378 {"amair_el3", AMAIR_EL3}, 379 {"vbar_el1", VBAR_EL1}, 380 {"vbar_el2", VBAR_EL2}, 381 {"vbar_el3", VBAR_EL3}, 382 {"rmr_el1", RMR_EL1}, 383 {"rmr_el2", RMR_EL2}, 384 {"rmr_el3", RMR_EL3}, 385 {"contextidr_el1", CONTEXTIDR_EL1}, 386 {"tpidr_el0", TPIDR_EL0}, 387 {"tpidr_el2", TPIDR_EL2}, 388 {"tpidr_el3", TPIDR_EL3}, 389 {"tpidrro_el0", TPIDRRO_EL0}, 390 {"tpidr_el1", TPIDR_EL1}, 391 {"cntfrq_el0", CNTFRQ_EL0}, 392 {"cntvoff_el2", CNTVOFF_EL2}, 393 {"cntkctl_el1", CNTKCTL_EL1}, 394 {"cnthctl_el2", CNTHCTL_EL2}, 395 {"cntp_tval_el0", CNTP_TVAL_EL0}, 396 {"cnthp_tval_el2", CNTHP_TVAL_EL2}, 397 {"cntps_tval_el1", CNTPS_TVAL_EL1}, 398 {"cntp_ctl_el0", CNTP_CTL_EL0}, 399 {"cnthp_ctl_el2", CNTHP_CTL_EL2}, 400 {"cntps_ctl_el1", CNTPS_CTL_EL1}, 401 {"cntp_cval_el0", CNTP_CVAL_EL0}, 402 {"cnthp_cval_el2", CNTHP_CVAL_EL2}, 403 {"cntps_cval_el1", CNTPS_CVAL_EL1}, 404 {"cntv_tval_el0", CNTV_TVAL_EL0}, 405 {"cntv_ctl_el0", CNTV_CTL_EL0}, 406 {"cntv_cval_el0", CNTV_CVAL_EL0}, 407 {"pmevcntr0_el0", PMEVCNTR0_EL0}, 408 {"pmevcntr1_el0", PMEVCNTR1_EL0}, 409 {"pmevcntr2_el0", PMEVCNTR2_EL0}, 410 {"pmevcntr3_el0", PMEVCNTR3_EL0}, 411 {"pmevcntr4_el0", PMEVCNTR4_EL0}, 412 {"pmevcntr5_el0", PMEVCNTR5_EL0}, 413 {"pmevcntr6_el0", PMEVCNTR6_EL0}, 414 {"pmevcntr7_el0", PMEVCNTR7_EL0}, 415 {"pmevcntr8_el0", PMEVCNTR8_EL0}, 416 {"pmevcntr9_el0", PMEVCNTR9_EL0}, 417 {"pmevcntr10_el0", PMEVCNTR10_EL0}, 418 {"pmevcntr11_el0", PMEVCNTR11_EL0}, 419 {"pmevcntr12_el0", PMEVCNTR12_EL0}, 420 {"pmevcntr13_el0", PMEVCNTR13_EL0}, 421 {"pmevcntr14_el0", PMEVCNTR14_EL0}, 422 {"pmevcntr15_el0", PMEVCNTR15_EL0}, 423 {"pmevcntr16_el0", PMEVCNTR16_EL0}, 424 {"pmevcntr17_el0", PMEVCNTR17_EL0}, 425 {"pmevcntr18_el0", PMEVCNTR18_EL0}, 426 {"pmevcntr19_el0", PMEVCNTR19_EL0}, 427 {"pmevcntr20_el0", PMEVCNTR20_EL0}, 428 {"pmevcntr21_el0", PMEVCNTR21_EL0}, 429 {"pmevcntr22_el0", PMEVCNTR22_EL0}, 430 {"pmevcntr23_el0", PMEVCNTR23_EL0}, 431 {"pmevcntr24_el0", PMEVCNTR24_EL0}, 432 {"pmevcntr25_el0", PMEVCNTR25_EL0}, 433 {"pmevcntr26_el0", PMEVCNTR26_EL0}, 434 {"pmevcntr27_el0", PMEVCNTR27_EL0}, 435 {"pmevcntr28_el0", PMEVCNTR28_EL0}, 436 {"pmevcntr29_el0", PMEVCNTR29_EL0}, 437 {"pmevcntr30_el0", PMEVCNTR30_EL0}, 438 {"pmccfiltr_el0", PMCCFILTR_EL0}, 439 {"pmevtyper0_el0", PMEVTYPER0_EL0}, 440 {"pmevtyper1_el0", PMEVTYPER1_EL0}, 441 {"pmevtyper2_el0", PMEVTYPER2_EL0}, 442 {"pmevtyper3_el0", PMEVTYPER3_EL0}, 443 {"pmevtyper4_el0", PMEVTYPER4_EL0}, 444 {"pmevtyper5_el0", PMEVTYPER5_EL0}, 445 {"pmevtyper6_el0", PMEVTYPER6_EL0}, 446 {"pmevtyper7_el0", PMEVTYPER7_EL0}, 447 {"pmevtyper8_el0", PMEVTYPER8_EL0}, 448 {"pmevtyper9_el0", PMEVTYPER9_EL0}, 449 {"pmevtyper10_el0", PMEVTYPER10_EL0}, 450 {"pmevtyper11_el0", PMEVTYPER11_EL0}, 451 {"pmevtyper12_el0", PMEVTYPER12_EL0}, 452 {"pmevtyper13_el0", PMEVTYPER13_EL0}, 453 {"pmevtyper14_el0", PMEVTYPER14_EL0}, 454 {"pmevtyper15_el0", PMEVTYPER15_EL0}, 455 {"pmevtyper16_el0", PMEVTYPER16_EL0}, 456 {"pmevtyper17_el0", PMEVTYPER17_EL0}, 457 {"pmevtyper18_el0", PMEVTYPER18_EL0}, 458 {"pmevtyper19_el0", PMEVTYPER19_EL0}, 459 {"pmevtyper20_el0", PMEVTYPER20_EL0}, 460 {"pmevtyper21_el0", PMEVTYPER21_EL0}, 461 {"pmevtyper22_el0", PMEVTYPER22_EL0}, 462 {"pmevtyper23_el0", PMEVTYPER23_EL0}, 463 {"pmevtyper24_el0", PMEVTYPER24_EL0}, 464 {"pmevtyper25_el0", PMEVTYPER25_EL0}, 465 {"pmevtyper26_el0", PMEVTYPER26_EL0}, 466 {"pmevtyper27_el0", PMEVTYPER27_EL0}, 467 {"pmevtyper28_el0", PMEVTYPER28_EL0}, 468 {"pmevtyper29_el0", PMEVTYPER29_EL0}, 469 {"pmevtyper30_el0", PMEVTYPER30_EL0}, 470 }; 471 472 uint32_t 473 A64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const { 474 // First search the registers shared by all 475 std::string NameLower = Name.lower(); 476 for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) { 477 if (SysRegPairs[i].Name == NameLower) { 478 Valid = true; 479 return SysRegPairs[i].Value; 480 } 481 } 482 483 // Now try the instruction-specific registers (either read-only or 484 // write-only). 485 for (unsigned i = 0; i < NumInstPairs; ++i) { 486 if (InstPairs[i].Name == NameLower) { 487 Valid = true; 488 return InstPairs[i].Value; 489 } 490 } 491 492 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits 493 // are: 11 xxx 1x11 xxxx xxx 494 Regex GenericRegPattern("^s3_([0-7])_c(1[15])_c([0-9]|1[0-5])_([0-7])$"); 495 496 SmallVector<StringRef, 4> Ops; 497 if (!GenericRegPattern.match(NameLower, &Ops)) { 498 Valid = false; 499 return -1; 500 } 501 502 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 503 uint32_t Bits; 504 Ops[1].getAsInteger(10, Op1); 505 Ops[2].getAsInteger(10, CRn); 506 Ops[3].getAsInteger(10, CRm); 507 Ops[4].getAsInteger(10, Op2); 508 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 509 510 Valid = true; 511 return Bits; 512 } 513 514 std::string 515 A64SysReg::SysRegMapper::toString(uint32_t Bits, bool &Valid) const { 516 for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) { 517 if (SysRegPairs[i].Value == Bits) { 518 Valid = true; 519 return SysRegPairs[i].Name; 520 } 521 } 522 523 for (unsigned i = 0; i < NumInstPairs; ++i) { 524 if (InstPairs[i].Value == Bits) { 525 Valid = true; 526 return InstPairs[i].Name; 527 } 528 } 529 530 uint32_t Op0 = (Bits >> 14) & 0x3; 531 uint32_t Op1 = (Bits >> 11) & 0x7; 532 uint32_t CRn = (Bits >> 7) & 0xf; 533 uint32_t CRm = (Bits >> 3) & 0xf; 534 uint32_t Op2 = Bits & 0x7; 535 536 // Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic 537 // name. 538 if (Op0 != 3 || (CRn != 11 && CRn != 15)) { 539 Valid = false; 540 return ""; 541 } 542 543 assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg"); 544 545 Valid = true; 546 return "s3_" + utostr(Op1) + "_c" + utostr(CRn) 547 + "_c" + utostr(CRm) + "_" + utostr(Op2); 548 } 549 550 const NamedImmMapper::Mapping A64TLBI::TLBIMapper::TLBIPairs[] = { 551 {"ipas2e1is", IPAS2E1IS}, 552 {"ipas2le1is", IPAS2LE1IS}, 553 {"vmalle1is", VMALLE1IS}, 554 {"alle2is", ALLE2IS}, 555 {"alle3is", ALLE3IS}, 556 {"vae1is", VAE1IS}, 557 {"vae2is", VAE2IS}, 558 {"vae3is", VAE3IS}, 559 {"aside1is", ASIDE1IS}, 560 {"vaae1is", VAAE1IS}, 561 {"alle1is", ALLE1IS}, 562 {"vale1is", VALE1IS}, 563 {"vale2is", VALE2IS}, 564 {"vale3is", VALE3IS}, 565 {"vmalls12e1is", VMALLS12E1IS}, 566 {"vaale1is", VAALE1IS}, 567 {"ipas2e1", IPAS2E1}, 568 {"ipas2le1", IPAS2LE1}, 569 {"vmalle1", VMALLE1}, 570 {"alle2", ALLE2}, 571 {"alle3", ALLE3}, 572 {"vae1", VAE1}, 573 {"vae2", VAE2}, 574 {"vae3", VAE3}, 575 {"aside1", ASIDE1}, 576 {"vaae1", VAAE1}, 577 {"alle1", ALLE1}, 578 {"vale1", VALE1}, 579 {"vale2", VALE2}, 580 {"vale3", VALE3}, 581 {"vmalls12e1", VMALLS12E1}, 582 {"vaale1", VAALE1} 583 }; 584 585 A64TLBI::TLBIMapper::TLBIMapper() 586 : NamedImmMapper(TLBIPairs, 0) {} 587 588 bool A64Imms::isFPImm(const APFloat &Val, uint32_t &Imm8Bits) { 589 const fltSemantics &Sem = Val.getSemantics(); 590 unsigned FracBits = APFloat::semanticsPrecision(Sem) - 1; 591 592 uint32_t ExpMask; 593 switch (FracBits) { 594 case 10: // IEEE half-precision 595 ExpMask = 0x1f; 596 break; 597 case 23: // IEEE single-precision 598 ExpMask = 0xff; 599 break; 600 case 52: // IEEE double-precision 601 ExpMask = 0x7ff; 602 break; 603 case 112: // IEEE quad-precision 604 // No immediates are valid for double precision. 605 return false; 606 default: 607 llvm_unreachable("Only half, single and double precision supported"); 608 } 609 610 uint32_t ExpStart = FracBits; 611 uint64_t FracMask = (1ULL << FracBits) - 1; 612 613 uint32_t Sign = Val.isNegative(); 614 615 uint64_t Bits= Val.bitcastToAPInt().getLimitedValue(); 616 uint64_t Fraction = Bits & FracMask; 617 int32_t Exponent = ((Bits >> ExpStart) & ExpMask); 618 Exponent -= ExpMask >> 1; 619 620 // S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>, 5):imm8<5:0>:Zeros(19) 621 // D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>, 8):imm8<5:0>:Zeros(48) 622 // This translates to: only 4 bits of fraction; -3 <= exp <= 4. 623 uint64_t A64FracStart = FracBits - 4; 624 uint64_t A64FracMask = 0xf; 625 626 // Are there too many fraction bits? 627 if (Fraction & ~(A64FracMask << A64FracStart)) 628 return false; 629 630 if (Exponent < -3 || Exponent > 4) 631 return false; 632 633 uint32_t PackedFraction = (Fraction >> A64FracStart) & A64FracMask; 634 uint32_t PackedExp = (Exponent + 7) & 0x7; 635 636 Imm8Bits = (Sign << 7) | (PackedExp << 4) | PackedFraction; 637 return true; 638 } 639 640 // Encoding of the immediate for logical (immediate) instructions: 641 // 642 // | N | imms | immr | size | R | S | 643 // |---+--------+--------+------+--------------+--------------| 644 // | 1 | ssssss | rrrrrr | 64 | UInt(rrrrrr) | UInt(ssssss) | 645 // | 0 | 0sssss | xrrrrr | 32 | UInt(rrrrr) | UInt(sssss) | 646 // | 0 | 10ssss | xxrrrr | 16 | UInt(rrrr) | UInt(ssss) | 647 // | 0 | 110sss | xxxrrr | 8 | UInt(rrr) | UInt(sss) | 648 // | 0 | 1110ss | xxxxrr | 4 | UInt(rr) | UInt(ss) | 649 // | 0 | 11110s | xxxxxr | 2 | UInt(r) | UInt(s) | 650 // | 0 | 11111x | - | | UNALLOCATED | | 651 // 652 // Columns 'R', 'S' and 'size' specify a "bitmask immediate" of size bits in 653 // which the lower S+1 bits are ones and the remaining bits are zero, then 654 // rotated right by R bits, which is then replicated across the datapath. 655 // 656 // + Values of 'N', 'imms' and 'immr' which do not match the above table are 657 // RESERVED. 658 // + If all 's' bits in the imms field are set then the instruction is 659 // RESERVED. 660 // + The 'x' bits in the 'immr' field are IGNORED. 661 662 bool A64Imms::isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits) { 663 int RepeatWidth; 664 int Rotation = 0; 665 int Num1s = 0; 666 667 // Because there are S+1 ones in the replicated mask, an immediate of all 668 // zeros is not allowed. Filtering it here is probably more efficient. 669 if (Imm == 0) return false; 670 671 for (RepeatWidth = RegWidth; RepeatWidth > 1; RepeatWidth /= 2) { 672 uint64_t RepeatMask = RepeatWidth == 64 ? -1 : (1ULL << RepeatWidth) - 1; 673 uint64_t ReplicatedMask = Imm & RepeatMask; 674 675 if (ReplicatedMask == 0) continue; 676 677 // First we have to make sure the mask is actually repeated in each slot for 678 // this width-specifier. 679 bool IsReplicatedMask = true; 680 for (unsigned i = RepeatWidth; i < RegWidth; i += RepeatWidth) { 681 if (((Imm >> i) & RepeatMask) != ReplicatedMask) { 682 IsReplicatedMask = false; 683 break; 684 } 685 } 686 if (!IsReplicatedMask) continue; 687 688 // Now we have to work out the amount of rotation needed. The first part of 689 // this calculation is actually independent of RepeatWidth, but the complex 690 // case will depend on it. 691 Rotation = CountTrailingZeros_64(Imm); 692 if (Rotation == 0) { 693 // There were no leading zeros, which means it's either in place or there 694 // are 1s at each end (e.g. 0x8003 needs rotating). 695 Rotation = RegWidth == 64 ? CountLeadingOnes_64(Imm) 696 : CountLeadingOnes_32(Imm); 697 Rotation = RepeatWidth - Rotation; 698 } 699 700 uint64_t ReplicatedOnes = (ReplicatedMask >> Rotation) 701 | ((ReplicatedMask << (RepeatWidth - Rotation)) & RepeatMask); 702 // Of course, they may not actually be ones, so we have to check that: 703 if (!isMask_64(ReplicatedOnes)) 704 continue; 705 706 Num1s = CountTrailingOnes_64(ReplicatedOnes); 707 708 // We know we've got an almost valid encoding (certainly, if this is invalid 709 // no other parameters would work). 710 break; 711 } 712 713 // The encodings which would produce all 1s are RESERVED. 714 if (RepeatWidth == 1 || Num1s == RepeatWidth) return false; 715 716 uint32_t N = RepeatWidth == 64; 717 uint32_t ImmR = RepeatWidth - Rotation; 718 uint32_t ImmS = Num1s - 1; 719 720 switch (RepeatWidth) { 721 default: break; // No action required for other valid rotations. 722 case 16: ImmS |= 0x20; break; // 10ssss 723 case 8: ImmS |= 0x30; break; // 110sss 724 case 4: ImmS |= 0x38; break; // 1110ss 725 case 2: ImmS |= 0x3c; break; // 11110s 726 } 727 728 Bits = ImmS | (ImmR << 6) | (N << 12); 729 730 return true; 731 } 732 733 734 bool A64Imms::isLogicalImmBits(unsigned RegWidth, uint32_t Bits, 735 uint64_t &Imm) { 736 uint32_t N = Bits >> 12; 737 uint32_t ImmR = (Bits >> 6) & 0x3f; 738 uint32_t ImmS = Bits & 0x3f; 739 740 // N=1 encodes a 64-bit replication and is invalid for the 32-bit 741 // instructions. 742 if (RegWidth == 32 && N != 0) return false; 743 744 int Width = 0; 745 if (N == 1) 746 Width = 64; 747 else if ((ImmS & 0x20) == 0) 748 Width = 32; 749 else if ((ImmS & 0x10) == 0) 750 Width = 16; 751 else if ((ImmS & 0x08) == 0) 752 Width = 8; 753 else if ((ImmS & 0x04) == 0) 754 Width = 4; 755 else if ((ImmS & 0x02) == 0) 756 Width = 2; 757 else { 758 // ImmS is 0b11111x: UNALLOCATED 759 return false; 760 } 761 762 int Num1s = (ImmS & (Width - 1)) + 1; 763 764 // All encodings which would map to -1 (signed) are RESERVED. 765 if (Num1s == Width) return false; 766 767 int Rotation = (ImmR & (Width - 1)); 768 uint64_t Mask = (1ULL << Num1s) - 1; 769 uint64_t WidthMask = Width == 64 ? -1 : (1ULL << Width) - 1; 770 Mask = (Mask >> Rotation) 771 | ((Mask << (Width - Rotation)) & WidthMask); 772 773 Imm = 0; 774 for (unsigned i = 0; i < RegWidth / Width; ++i) { 775 Imm |= Mask; 776 Mask <<= Width; 777 } 778 779 return true; 780 } 781 782 bool A64Imms::isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) { 783 // If high bits are set then a 32-bit MOVZ can't possibly work. 784 if (RegWidth == 32 && (Value & ~0xffffffffULL)) 785 return false; 786 787 for (int i = 0; i < RegWidth; i += 16) { 788 // If the value is 0 when we mask out all the bits that could be set with 789 // the current LSL value then it's representable. 790 if ((Value & ~(0xffffULL << i)) == 0) { 791 Shift = i / 16; 792 UImm16 = (Value >> i) & 0xffff; 793 return true; 794 } 795 } 796 return false; 797 } 798 799 bool A64Imms::isMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) { 800 // MOVN is defined to set its register to NOT(LSL(imm16, shift)). 801 802 // We have to be a little careful about a 32-bit register: 0xffff_1234 *is* 803 // representable, but ~0xffff_1234 == 0xffff_ffff_0000_edcb which is not 804 // a valid input for isMOVZImm. 805 if (RegWidth == 32 && (Value & ~0xffffffffULL)) 806 return false; 807 808 uint64_t MOVZEquivalent = RegWidth == 32 ? ~Value & 0xffffffff : ~Value; 809 810 return isMOVZImm(RegWidth, MOVZEquivalent, UImm16, Shift); 811 } 812 813 bool A64Imms::isOnlyMOVNImm(int RegWidth, uint64_t Value, 814 int &UImm16, int &Shift) { 815 if (isMOVZImm(RegWidth, Value, UImm16, Shift)) 816 return false; 817 818 return isMOVNImm(RegWidth, Value, UImm16, Shift); 819 } 820
