| /external/v8/src/arm/ |
| constants-arm.h | 280 CPSR = 0 << 22,
303 CPSR_c = CPSR | 1 << 16,
304 CPSR_x = CPSR | 1 << 17,
305 CPSR_s = CPSR | 1 << 18,
306 CPSR_f = CPSR | 1 << 19,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 52 // 2 - Always set CPSR.
82 // FIXME: tMOVi8 and tMVN also partially update CPSR but they are less
205 if (*Regs == ARM::CPSR)
211 /// the 's' 16-bit instruction partially update CPSR. Abort the
212 /// transformation to avoid adding false dependency on last CPSR setting
216 /// last instruction that defines the CPSR and the current instruction. If there
218 /// before the CPSR setting instruction anyway.
245 if (Reg == 0 || Reg == ARM::CPSR)
270 // Not predicated, must set CPSR.
272 // Original instruction was not setting CPSR, but CPSR is no
[all...] |
| ARMMCInstLower.cpp | 71 // Ignore all non-CPSR implicit register operands.
72 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
|
| Thumb2ITBlockPass.cpp | 86 if (Reg == ARM::CPSR)
124 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
|
| ARMBaseInstrInfo.cpp | 515 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
516 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
[all...] |
| ARMFastISel.cpp | 223 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
236 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
237 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
241 // Look to see if our OptionalDef is defining CPSR or CCR.
245 if (MO.getReg() == ARM::CPSR)
246 *CPSR = true;
269 // CPSR defs that need to be added before the remaining operands. See s_cc_out
282 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
283 bool CPSR = false
[all...] |
| ARMBaseInstrInfo.h | 332 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
376 /// CPSR def operand.
|
| ARMISelLowering.cpp | [all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMCodeEmitter.cpp | 828 // Encode S bit if MI modifies CPSR.
856 // Encode S bit if MI modifies CPSR.
[all...] |
| ARMLoadStoreOptimizer.cpp | 520 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
521 // If the instruction has live CPSR def, then it's not safe to fold it
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 617 // implicitly set CPSR. Since it's not represented in the encoding, the
618 // auto-generated decoder won't inject the CPSR operand. We need to fix
628 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
633 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
697 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
707 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 234 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
236 return MI.getOperand(Op).getReg() == ARM::CPSR;
560 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 827 O << "CPSR";
858 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
859 "Expect ARM CPSR register!");
[all...] |
