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    Searched refs:Orders (Results 1 - 4 of 4) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 705 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
723 Orders.push_back(std::make_pair(DVOrder, DbgMI));
737 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
743 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
750 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
754 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
755 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
803 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
843 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
850 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
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  /external/llvm/utils/TableGen/
CodeGenRegisters.h 231 // Allocation orders. Order[0] always contains all registers in Members.
232 std::vector<SmallVector<Record*, 16> > Orders;
339 return Orders[No];
342 // Return the total number of allocation orders available.
343 unsigned getNumOrders() const { return Orders.size(); }
CodeGenRegisters.cpp 724 Orders.resize(1 + AltOrders->size());
728 Orders[0].push_back((*Elements)[i]);
734 // Alternative allocation orders may be subsets.
738 Orders[1 + i].append(Order.begin(), Order.end());
795 // Copy all allocation orders, filter out foreign registers from the larger
797 Orders.resize(Super.Orders.size());
798 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
799 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
800 if (contains(RegBank.getReg(Super.Orders[i][j]))
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  /external/clang/lib/CodeGen/
CGBuiltin.cpp     [all...]

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