| /external/qemu/ |
| ppc-dis.c | 688 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
689 #define RA NSI + 1
693 /* As above, but 0 in the RA field means zero, not r0. */
694 #define RA0 RA + 1
697 /* The RA field in the DQ form lq instruction, which has special
702 /* The RA field in a D or X form instruction which is an updating
703 load, which means that the RA field may not be zero and may not
708 /* The RA field in an lmw instruction, which has special value
713 /* The RA field in a D or X form instruction which is an updating
714 store or an updating floating point load, which means that the RA
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 397 #define RA(r) ((r)<<16)
407 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
408 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
451 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
461 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
464 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
493 tcg_out32 (s, LWZ | RT (0) | RA (reg));
494 tcg_out32 (s, MTSPR | RA (0) | CTR)
[all...] |
| /external/smack/src/org/xbill/DNS/ |
| Flags.java | 29 public static final byte RA = 8;
49 flags.add(RA, "ra");
|
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 394 #define RA(r) ((r)<<16)
405 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
443 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
455 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16)
[all...] |
| /external/clang/test/CodeGenCXX/ |
| devirtualize-virtual-function-calls-final.cpp | 164 struct RA {
169 struct RC final : public RA {
185 return static_cast<RA*>(x)->f();
|
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 526 unsigned RA = getRA(insn);
539 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
543 instr.addOperand(MCOperand::CreateReg(RA));
547 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
550 instr.addOperand(MCOperand::CreateReg(RA));
555 if (RD == UNSUPPORTED || RA == UNSUPPORTED)
558 instr.addOperand(MCOperand::CreateReg(RA));
572 if (RA == UNSUPPORTED)
575 instr.addOperand(MCOperand::CreateReg(RA));
588 if (RD == UNSUPPORTED || RA == UNSUPPORTED
[all...] |
| /external/llvm/test/MC/MBlaze/ |
| mblaze_pattern.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| mblaze_shift.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| mblaze_fpu.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| /external/llvm/lib/MC/ |
| MCSubtargetInfo.cpp | 43 const MCReadAdvanceEntry *RA,
54 ReadAdvanceTable = RA;
|
| /bionic/libc/arch-mips/include/machine/ |
| regnum.h | 67 #define RA 31
|
| /development/ndk/platforms/android-9/arch-mips/include/machine/ |
| regnum.h | 67 #define RA 31
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/machine/ |
| regnum.h | 67 #define RA 31
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/machine/ |
| regnum.h | 67 #define RA 31
|
| /external/llvm/lib/Transforms/IPO/ |
| DeadArgumentElimination.cpp | 158 void MarkValue(const RetOrArg &RA, Liveness L,
160 void MarkLive(const RetOrArg &RA);
162 void PropagateLiveness(const RetOrArg &RA);
617 /// MarkValue - This function marks the liveness of RA depending on L. If L is
619 /// such that RA will be marked live if any use in MaybeLiveUses gets marked
621 void DAE::MarkValue(const RetOrArg &RA, Liveness L,
624 case Live: MarkLive(RA); break;
631 Uses.insert(std::make_pair(*UI, RA));
656 void DAE::MarkLive(const RetOrArg &RA) {
657 if (LiveFunctions.count(RA.F)
[all...] |
| /external/llvm/utils/TableGen/ |
| FixedLenDecoderEmitter.cpp | 468 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
150 // Reserve RA if in mips16 mode.
152 Reserved.set(Mips::RA);
|
| Mips16FrameLowering.cpp | 69 SrcML = MachineLocation(Mips::RA);
108 // Registers RA, S0,S1 are the callee saved registers and they
114 // RA and return address is taken, because it has already been added in
116 // It's killed at the spill, unless the register is RA and return address
119 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
133 // Registers RA,S0,S1 are the callee saved registers and they will be restored
172 MF.getRegInfo().setPhysRegUsed(Mips::RA);
|
| MipsSEInstrInfo.cpp | 329 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
373 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
378 // or $ra, $v0, $zero
380 // jr $ra
381 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA)
385 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 47 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
50 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
|
| /external/llvm/include/llvm/MC/ |
| MCSubtargetInfo.h | 55 const MCReadAdvanceEntry *RA,
|
| MCRegisterInfo.h | 235 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
247 RAReg = RA;
|
| /libcore/luni/src/test/java/libcore/java/util/ |
| EnumSetTest.java | 105 HF, TA, W, RE, OS, IR, PT, AU, HG, TL, PB, BI, PO, AT, RN, FR, RA, AC, TH, PA, U, NP, PU,
|
| /external/llvm/lib/Analysis/ |
| ScalarEvolution.cpp | 509 const Argument *RA = cast<Argument>(RV);
510 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo();
544 const APInt &RA = RC->getValue()->getValue();
545 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth();
548 return LA.ult(RA) ? -1 : 1;
553 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS);
556 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop();
565 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands();
571 long X = compare(LA->getOperand(i), RA->getOperand(i));
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 253 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
258 InitX86MCRegisterInfo(X, RA,
261 RA);
|
