| /external/valgrind/main/none/tests/s390x/ |
| opcodes.h | 47 #define RRS(op1,r1,r2,b4,d4,m3,u0,op2) \
132 #define CGRB(r1,r2,b4,d4,m3) RRS(ec,r1,r2,b4,d4,m3,0,e4)
153 #define CLGRB(r1,r2,b4,d4,m3) RRS(ec,r1,r2,b4,d4,m3,0,e5)
166 #define CLRB(r1,r2,b4,d4,m3) RRS(ec,r1,r2,b4,d4,m3,0,f7)
171 #define CRB(r1,r2,b4,d4,m3) RRS(ec,r1,r2,b4,d4,m3,0,f6)
|
| /external/valgrind/main/VEX/priv/ |
| host_arm_defs.h | 139 } RRS;
|
| host_arm_defs.c | 230 am->ARMam1.RRS.base = base;
231 am->ARMam1.RRS.index = index;
232 am->ARMam1.RRS.shift = shift;
246 ppHRegARM(am->ARMam1.RRS.base);
248 ppHRegARM(am->ARMam1.RRS.index);
249 vex_printf(",%u)", am->ARMam1.RRS.shift);
262 // addHRegUse(u, HRmRead, am->ARMam1.RRS.base);
263 // addHRegUse(u, HRmRead, am->ARMam1.RRS.index);
[all...] |
| guest_s390_toIR.c | [all...] |
| host_arm_isel.c | 661 toBool( hregClass(am->ARMam1.RRS.base) == HRcInt32
662 && hregIsVirtual(am->ARMam1.RRS.base)
663 && hregClass(am->ARMam1.RRS.index) == HRcInt32
664 && hregIsVirtual(am->ARMam1.RRS.index)
665 && am->ARMam1.RRS.shift >= 0
666 && am->ARMam1.RRS.shift <= 3 );
684 /* FIXME: add RRS matching */
[all...] |
