| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 77 bool IgnoreNodeResults(SDNode *N) const {
116 SmallVector<SDNode*, 128> Worklist;
131 void NoteDeletion(SDNode *Old, SDNode *New) {
141 SDNode *AnalyzeNewNode(SDNode *N);
143 void ExpungeNode(SDNode *N);
151 bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
152 bool CustomWidenLowerNode(SDNode *N, EVT VT);
157 SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo)
[all...] |
| SDNodeOrdering.h | 1 //===-- llvm/CodeGen/SDNodeOrdering.h - SDNode Ordering ---------*- C++ -*-===//
21 class SDNode;
24 /// SDNode that roughly corresponds to the ordering of the original LLVM
29 DenseMap<const SDNode*, unsigned> OrderMap;
36 void add(const SDNode *Node, unsigned O) {
39 void remove(const SDNode *Node) {
40 DenseMap<const SDNode*, unsigned>::iterator Itr = OrderMap.find(Node);
47 unsigned getOrder(const SDNode *Node) {
|
| InstrEmitter.h | 42 void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
49 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node,
52 void CreateVirtualRegisters(SDNode *Node,
92 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
99 void EmitCopyToRegClassNode(SDNode *Node,
104 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
110 static unsigned CountResults(SDNode *Node);
119 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
138 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
140 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned
[all...] |
| SelectionDAGPrinter.cpp | 43 return ((const SDNode *) Node)->getNumValues();
47 return ((const SDNode *) Node)->getValueType(i).getEVTString();
52 return itostr(I - SDNodeIterator::begin((const SDNode *) Node));
68 SDNode *TargetNode = *I;
82 static bool hasNodeAddressLabel(const SDNode *Node,
102 static std::string getSimpleNodeLabel(const SDNode *Node,
111 std::string getNodeLabel(const SDNode *Node, const SelectionDAG *Graph);
112 static std::string getNodeAttributes(const SDNode *N,
136 std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
176 void SelectionDAG::setGraphAttrs(const SDNode *N, const char *Attrs)
[all...] |
| ScheduleDAGSDNodes.h | 1 //===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
11 // scheduling for an SDNode-based dependency graph.
22 /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
32 /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
55 static bool isPassiveNode(SDNode *Node) {
75 SUnit *newSUnit(SDNode *N);
102 virtual void computeOperandLatency(SDNode *Def, SDNode *Use,
135 const SDNode *Node;
149 const SDNode *GetNode() const
[all...] |
| SDNodeDbgValue.h | 24 class SDNode;
33 SDNODE = 0, // value is the result of an expression
41 SDNode *Node; // valid for expressions
54 SDDbgValue(MDNode *mdP, SDNode *N, unsigned R, uint64_t off, DebugLoc dl,
57 kind = SDNODE;
83 // Returns the SDNode* for a register ref
84 SDNode *getSDNode() { assert (kind==SDNODE); return u.s.Node; }
87 unsigned getResNo() { assert (kind==SDNODE); return u.s.ResNo; }
106 // property. A SDDbgValue is invalid if the SDNode that produces the value i
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| ScheduleDAGSDNodes.cpp | 68 SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
110 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
135 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG,
162 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
164 SDNode *GlueDestNode = Glue.getNode();
190 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
207 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
208 SDNode *Chain = 0;
217 SmallPtrSet<SDNode*, 16> Visited
[all...] |
| LegalizeFloatTypes.cpp | 47 void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
109 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N) {
113 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N,
119 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
134 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
141 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
153 SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
166 SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
178 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
220 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N)
[all...] |
| SelectionDAGDumper.cpp | 33 std::string SDNode::getOperationName(const SelectionDAG *G) const {
320 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
330 void SDNode::dump() const { dump(0); }
331 void SDNode::dump(const SelectionDAG *G) const {
336 void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const {
349 void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
516 static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
534 const SDNode *N = I;
543 void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const {
548 typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet
[all...] |
| SelectionDAG.cpp | 64 void SelectionDAG::DAGUpdateListener::NodeDeleted(SDNode*, SDNode*) {}
65 void SelectionDAG::DAGUpdateListener::NodeUpdated(SDNode*) {}
98 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
146 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
186 bool ISD::isScalarToVector(const SDNode *N) {
207 bool ISD::allOperandsUndef(const SDNode *N) {
321 // SDNode Profile Support
364 /// AddNodeIDCustom - If this is an SDNode with special info, add this info to
366 static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.h | 74 SDNode *Select(SDNode *N);
75 SDNode *SelectLoad(SDNode *N);
76 SDNode *SelectLoadVector(SDNode *N);
77 SDNode *SelectLDGLDUVector(SDNode *N);
78 SDNode *SelectStore(SDNode *N)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.h | 26 std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, DebugLoc DL,
31 void getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg);
33 virtual bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
36 virtual std::pair<bool, SDNode*> selectNode(SDNode *Node);
|
| MipsSEISelDAGToDAG.h | 29 std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
32 SDNode *selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
33 DebugLoc DL, SDNode *Node) const;
44 virtual std::pair<bool, SDNode*> selectNode(SDNode *Node);
|
| MipsISelDAGToDAG.h | 45 SDNode *getGlobalBaseReg();
68 virtual bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
71 virtual SDNode *Select(SDNode *N);
73 virtual std::pair<bool, SDNode*> selectNode(SDNode *Node) = 0;
76 inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
|
| MipsISelDAGToDAG.cpp | 59 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
84 bool MipsDAGToDAGISel::selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
92 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
105 std::pair<bool, SDNode*> Ret = selectNode(Node);
128 SDNode *ResNode = SelectCode(Node);
|
| Mips16ISelDAGToDAG.cpp | 39 std::pair<SDNode*, SDNode*>
40 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty,
42 SDNode *Lo = 0, *Hi = 0;
43 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
119 void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
153 SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
231 std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
270 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops, 2)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGISel.h | 80 virtual SDNode *Select(SDNode *N) = 0;
95 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
101 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
191 void ReplaceUses(SDNode *F, SDNode *T) {
221 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
225 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N
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| SelectionDAG.h | 11 // SDNode class and subclasses.
42 template<> struct ilist_traits<SDNode> : public ilist_default_traits<SDNode> {
44 mutable ilist_half_node<SDNode> Sentinel;
46 SDNode *createSentinel() const {
47 return static_cast<SDNode*>(&Sentinel);
49 static void destroySentinel(SDNode *) {}
51 SDNode *provideInitialHead() const { return createSentinel(); }
52 SDNode *ensureHead(SDNode*) const { return createSentinel();
[all...] |
| SelectionDAGNodes.h | 10 // This file declares the SDNode class and derived classes, which are used to
44 class SDNode;
51 void checkForCycles(const SDNode *N);
67 bool isBuildVectorAllOnes(const SDNode *N);
71 bool isBuildVectorAllZeros(const SDNode *N);
76 bool isScalarToVector(const SDNode *N);
80 bool allOperandsUndef(const SDNode *N);
95 SDNode *Node; // The node defining the value we are using.
99 SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno) {}
101 /// get the index which selects a specific result in the SDNode
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 118 SDNode *Select(SDNode *N);
119 SDNode *SelectIndexedLoad(SDNode *Op);
120 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
329 SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
353 SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 64 bool hasNumUsesBelowThresGA(SDNode *N) const;
66 SDNode *Select(SDNode *N);
92 bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
94 SDNode *SelectLoad(SDNode *N);
95 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl);
96 SDNode *SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl);
97 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
99 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.h | 53 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
54 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
56 int32_t analyzeImmediate(const SDNode *N) const;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 91 SDNode *TrySelectToMoveImm(SDNode *N);
92 SDNode *LowerToFPLitPool(SDNode *Node);
93 SDNode *SelectToLitPool(SDNode *N);
95 SDNode* Select(SDNode*);
176 SDNode *AArch64DAGToDAGISel::TrySelectToMoveImm(SDNode *Node)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 81 SDNode *getGlobalBaseReg();
82 SDNode *Select(SDNode *N);
100 static bool isIntS32Immediate(SDNode *N, int32_t &Imm) {
182 SDNode *MBlazeDAGToDAGISel::getGlobalBaseReg() {
189 SDNode* MBlazeDAGToDAGISel::Select(SDNode *Node) {
250 SDNode *ResNode = CurDAG->getMachineNode(MBlaze::BRLID, dl, MVT::Other,
262 SDNode *ResNode = SelectCode(Node);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 49 SDNode *Select(SDNode *N);
50 SDNode *SelectBRIND(SDNode *N);
58 inline bool immMskBitp(SDNode *inN) const {
155 SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
173 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
220 if (SDNode *ResNode = SelectBRIND(N))
255 SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N)
[all...] |
