1 //===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines an instruction selector for the NVPTX target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "nvptx-isel" 15 16 #include "NVPTX.h" 17 #include "NVPTXISelLowering.h" 18 #include "NVPTXRegisterInfo.h" 19 #include "NVPTXTargetMachine.h" 20 #include "llvm/CodeGen/SelectionDAGISel.h" 21 #include "llvm/IR/Intrinsics.h" 22 #include "llvm/Support/Compiler.h" 23 using namespace llvm; 24 25 namespace { 26 27 class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel { 28 29 // If true, generate corresponding FPCONTRACT. This is 30 // language dependent (i.e. CUDA and OpenCL works differently). 31 bool doFMADF32; 32 bool doFMAF64; 33 bool doFMAF32; 34 bool doFMAF64AGG; 35 bool doFMAF32AGG; 36 bool allowFMA; 37 38 // 0: use div.approx 39 // 1: use div.full 40 // 2: For sm_20 and later, ieee-compliant div.rnd.f32 can be generated; 41 // Otherwise, use div.full 42 int do_DIVF32_PREC; 43 44 // If true, add .ftz to f32 instructions. 45 // This is only meaningful for sm_20 and later, as the default 46 // is not ftz. 47 // For sm earlier than sm_20, f32 denorms are always ftz by the 48 // hardware. 49 // We always add the .ftz modifier regardless of the sm value 50 // when Use32FTZ is true. 51 bool UseF32FTZ; 52 53 // If true, generate mul.wide from sext and mul 54 bool doMulWide; 55 56 public: 57 explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, 58 CodeGenOpt::Level OptLevel); 59 60 // Pass Name 61 virtual const char *getPassName() const { 62 return "NVPTX DAG->DAG Pattern Instruction Selection"; 63 } 64 65 const NVPTXSubtarget &Subtarget; 66 67 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 68 char ConstraintCode, 69 std::vector<SDValue> &OutOps); 70 private: 71 // Include the pieces autogenerated from the target description. 72 #include "NVPTXGenDAGISel.inc" 73 74 SDNode *Select(SDNode *N); 75 SDNode *SelectLoad(SDNode *N); 76 SDNode *SelectLoadVector(SDNode *N); 77 SDNode *SelectLDGLDUVector(SDNode *N); 78 SDNode *SelectStore(SDNode *N); 79 SDNode *SelectStoreVector(SDNode *N); 80 81 inline SDValue getI32Imm(unsigned Imm) { 82 return CurDAG->getTargetConstant(Imm, MVT::i32); 83 } 84 85 // Match direct address complex pattern. 86 bool SelectDirectAddr(SDValue N, SDValue &Address); 87 88 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base, 89 SDValue &Offset, MVT mvt); 90 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base, 91 SDValue &Offset); 92 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base, 93 SDValue &Offset); 94 95 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base, 96 SDValue &Offset, MVT mvt); 97 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base, 98 SDValue &Offset); 99 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base, 100 SDValue &Offset); 101 102 103 bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const; 104 105 bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval); 106 107 }; 108 } 109
