| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr;
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 399 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
510 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
542 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
[all...] |
| MIPSAssembler.h | 317 void SRA(int Rd, int Rt, int shft);
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 318 SHL, SRA, SRL, ROTL, ROTR,
382 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 95 setOperationAction(ISD::SRA, MVT::i8, Custom);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
191 case ISD::SRA: return LowerShifts(Op, DAG);
637 case ISD::SRA:
638 return DAG.getNode(MSP430ISD::SRA, dl,
[all...] |
| /external/v8/src/mips/ |
| constants-mips.cc | 245 case SRA:
|
| constants-mips.h | 306 SRA = ((0 << 3) + 3),
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
561 return DAG.getNode(ISD::SRA, N->getDebugLoc(), Res.getValueType(), Res, Amt);
[all...] |
| LegalizeVectorOps.cpp | 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
64 // Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
209 case ISD::SRA:
485 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
635 // Make sure that the SRA and SHL instructions are available.
636 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
649 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
|
| FastISel.cpp | 412 // Transform "sdiv exact X, 8" -> "sra X, 3".
417 ISDOpcode = ISD::SRA;
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGBuilder.h | 491 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
|
| SelectionDAGDumper.cpp | 173 case ISD::SRA: return "sra";
|
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorTypes.cpp | 114 case ISD::SRA:
567 case ISD::SRA:
[all...] |
| TargetLowering.cpp | 685 case ISD::SRA:
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 91 SRL, SRA, SHL,
|
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 352 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
419 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
|
| /external/llvm/lib/TableGen/ |
| Record.cpp | 940 case SRA:
951 case SRA: Result = LHSv >> RHSv; break;
977 case SRA: Result = "!sra"; break;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 498 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 122 case 0x01: return MBlaze::SRA;
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 729 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
738 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 269 // sra dst, dst
325 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
449 // sra dst, dst
[all...] |
