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      1 /*
      2  *  Copyright 2001-2008 Texas Instruments - http://www.ti.com/
      3  *
      4  *  Licensed under the Apache License, Version 2.0 (the "License");
      5  *  you may not use this file except in compliance with the License.
      6  *  You may obtain a copy of the License at
      7  *
      8  *     http://www.apache.org/licenses/LICENSE-2.0
      9  *
     10  *  Unless required by applicable law or agreed to in writing, software
     11  *  distributed under the License is distributed on an "AS IS" BASIS,
     12  *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     13  *  See the License for the specific language governing permissions and
     14  *  limitations under the License.
     15  */
     16 
     17 /*
     18  *  ======== cfgdefs.h ========
     19  *  DSP-BIOS Bridge driver support functions for TI OMAP processors.
     20  *  Purpose:
     21  *      Global CFG constants and types, shared between class and mini driver.
     22  *
     23  *! Revision History:
     24  *! ================
     25  *! 24-Feb-2003 kc  Removed wIOPort* in CFG_HOSTRES.
     26  *! 06-Sep-2000 jeh Added channel info to CFG_HOSTRES.
     27  *! 09-May-2000 rr: CFG_HOSTRES now support multiple windows for PCI support.
     28  *! 31-Jan-2000 rr: Comments changed after code review.
     29  *! 06-Jan-2000 rr: Bus Type included in CFG_HOSTRES.
     30  *! 12-Nov-1999 rr: CFG_HOSTRES member names changed.
     31  *! 25-Oct-1999 rr: Modified the CFG_HOSTRES Structure
     32  *!                 PCMCIA ISR Register/Unregister fxn removed..
     33  *!                 New flag PCCARD introduced during compile time.
     34  *! 10-Sep-1999 ww: Added PCMCIA ISR Register/Unregister fxn.
     35  *! 01-Sep-1999 ag: Removed NT/95 specific fields in CFG_HOSTRES
     36  *! 27-Oct-1997 cr: Updated CFG_HOSTRES struct to support 1+ IRQs per board.
     37  *! 17-Sep-1997 gp: Tacked some NT config info to end of CFG_HOSTRES structure.
     38  *! 12-Dec-1996 cr: Cleaned up after code review.
     39  *! 14-Nov-1996 gp: Renamed from wsxcfg.h
     40  *! 19-Jun-1996 cr: Created.
     41  */
     42 
     43 #ifndef CFGDEFS_
     44 #define CFGDEFS_
     45 
     46 #ifdef __cplusplus
     47 extern "C" {
     48 #endif
     49 
     50 /* Maximum length of module search path. */
     51 #define CFG_MAXSEARCHPATHLEN    255
     52 
     53 /* Maximum length of general paths. */
     54 #define CFG_MAXPATH             255
     55 
     56 /* Host Resources:  */
     57 #define CFG_MAXMEMREGISTERS     9
     58 #define CFG_MAXIOPORTS          20
     59 #define CFG_MAXIRQS             7
     60 #define CFG_MAXDMACHANNELS      7
     61 
     62 /* IRQ flag */
     63 #define CFG_IRQSHARED           0x01	/* IRQ can be shared */
     64 
     65 /* DSP Resources: */
     66 #define CFG_DSPMAXMEMTYPES      10
     67 #define CFG_DEFAULT_NUM_WINDOWS 1	/* We support only one window. */
     68 
     69 /* A platform-related device handle: */
     70 	/*typedef struct CFG_DEVNODE *CFG_HDEVNODE;*/
     71 	struct CFG_DEVNODE;
     72 
     73 /*
     74  *  Host resource structure.
     75  */
     76 	struct CFG_HOSTRES {
     77 		DWORD wNumMemWindows;	/* Set to default */
     78 		/* This is the base.memory */
     79 		DWORD dwMemBase[CFG_MAXMEMREGISTERS];	/* SHM virtual address */
     80 		DWORD dwMemLength[CFG_MAXMEMREGISTERS];	/* Length of the  Base */
     81 		DWORD dwMemPhys[CFG_MAXMEMREGISTERS];	/* SHM Physical address */
     82 		BYTE bIRQRegisters;	/* IRQ Number */
     83 		BYTE bIRQAttrib;	/* IRQ Attribute */
     84 		DWORD dwOffsetForMonitor;	/* The Shared memory starts from
     85 						 * dwMemBase + this offset
     86 						 */
     87 		DWORD dwBusType;	/* Bus type for this device */
     88 		DWORD dwProgBase;	/* DSP ProgBase */
     89 		DWORD dwProgLength;	/* DSP ProgBase Length */
     90 		DWORD dwRegBase;	/* DSP memory mapped register base */
     91 		DWORD dwRegLength;	/* DSP Register Base Length */
     92 		DWORD ClientHandle;	/* Client Handle */
     93 		DWORD SocketHandle;	/* Socket and Function Pair */
     94 		DWORD CardInfo;	/* This will be used as a context data in
     95 				 * in the CardRequestIRQ
     96 				 */
     97 		/*
     98 		 *  Info needed by NODE for allocating channels to communicate with RMS:
     99 		 *      dwChnlOffset:       Offset of RMS channels. Lower channels are
    100 		 *                          reserved.
    101 		 *      dwChnlBufSize:      Size of channel buffer to send to RMS
    102 		 *      dwNumChnls:       Total number of channels (including reserved).
    103 		 */
    104 		DWORD dwChnlOffset;
    105 		DWORD dwChnlBufSize;
    106 		DWORD dwNumChnls;
    107 
    108 #ifdef OMAP_2430
    109 		DWORD dwPrcmBase;
    110 		DWORD dwWdTimerDspBase;
    111 		DWORD dwMboxBase;
    112 		DWORD dwDmmuBase;
    113 		DWORD dwDipiBase;
    114 		DWORD dwSysCtrlBase;
    115 #endif
    116 
    117 #ifdef OMAP_3430
    118 		DWORD dwPrmBase;
    119 		DWORD dwCmBase;
    120 		DWORD dwPerBase;
    121 		DWORD dwWdTimerDspBase;
    122 		DWORD dwMboxBase;
    123 		DWORD dwDmmuBase;
    124 		DWORD dwDipiBase;
    125 		DWORD dwSysCtrlBase;
    126 #endif
    127 	} ;
    128 
    129 	struct CFG_DSPMEMDESC {
    130 		UINT uMemType;	/* Type of memory.                        */
    131 		ULONG ulMin;	/* Minimum amount of memory of this type. */
    132 		ULONG ulMax;	/* Maximum amount of memory of this type. */
    133 	} ;
    134 
    135 	struct CFG_DSPRES {
    136 		UINT uChipType;	/* DSP chip type.               */
    137 		UINT uWordSize;	/* Number of bytes in a word    */
    138 		UINT cChips;	/* Number of chips.             */
    139 		UINT cMemTypes;	/* Types of memory.             */
    140 		struct CFG_DSPMEMDESC aMemDesc[CFG_DSPMAXMEMTYPES];
    141 		/* DSP Memory types */
    142 	} ;
    143 
    144 #ifdef __cplusplus
    145 }
    146 #endif
    147 #endif				/* CFGDEFS_ */
    148