| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 38 DestName = getRegName(MI->getOperand(0).getReg());
39 Src1Name = getRegName(MI->getOperand(1).getReg());
40 Src2Name = getRegName(MI->getOperand(2).getReg());
41 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
46 Src2Name = getRegName(MI->getOperand(2).getReg());
47 Src1Name = getRegName(MI->getOperand(1).getReg());
48 DestName = getRegName(MI->getOperand(0).getReg());
54 Src2Name = getRegName(MI->getOperand(2).getReg());
55 Src1Name = getRegName(MI->getOperand(1).getReg());
56 DestName = getRegName(MI->getOperand(0).getReg())
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsDirectObjLower.cpp | 26 assert(Inst.getOperand(2).isImm());
28 int64_t Shift = Inst.getOperand(2).getImm();
34 Inst.getOperand(2).setImm(Shift);
63 assert(InstIn.getOperand(2).isImm());
64 int64_t pos = InstIn.getOperand(2).getImm();
65 assert(InstIn.getOperand(3).isImm());
66 int64_t size = InstIn.getOperand(3).getImm();
72 InstIn.getOperand(2).setImm(pos - 32);
78 InstIn.getOperand(3).setImm(size - 32);
|
| /external/llvm/unittests/IR/ |
| MDBuilderTest.cpp | 38 Value *Op = MD1->getOperand(0);
52 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(0)));
53 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(1)));
54 ConstantInt *C0 = cast<ConstantInt>(R1->getOperand(0));
55 ConstantInt *C1 = cast<ConstantInt>(R1->getOperand(1));
66 EXPECT_EQ(R0->getOperand(0), R0);
67 EXPECT_EQ(R1->getOperand(0), R1);
68 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == 0);
69 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == 0);
77 EXPECT_TRUE(isa<MDString>(R0->getOperand(0)))
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 101 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
102 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
116 Base = Addr.getOperand(0);
122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
123 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
126 Base = Addr.getOperand(0).getOperand(0);
137 Base = Addr.getOperand(0);
143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
144 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))
[all...] |
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
65 MI->getOperand(0).setReg(NewReg);
|
| /external/llvm/lib/IR/ |
| IntrinsicInst.cpp | 37 return CE->getOperand(0);
58 return MD->getOperand(0);
68 return cast<MDNode>(getArgOperand(0))->getOperand(0);
72 return cast<MDNode>(getArgOperand(0))->getOperand(0);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitTFRCondSets.cpp | 90 int DestReg = MI->getOperand(0).getReg();
91 int SrcReg1 = MI->getOperand(2).getReg();
92 int SrcReg2 = MI->getOperand(3).getReg();
108 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
112 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
120 int DestReg = MI->getOperand(0).getReg();
121 int SrcReg1 = MI->getOperand(2).getReg();
128 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
133 addReg(MI->getOperand(1).getReg()).
134 addImm(MI->getOperand(3).getImm())
[all...] |
| HexagonAsmPrinter.h | 71 int value = MI->getOperand(OpNo).getImm();
77 int value = MI->getOperand(OpNo).getImm();
83 const MachineOperand &MO1 = MI->getOperand(OpNo);
84 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
93 const MachineOperand &MO1 = MI->getOperand(OpNo);
94 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
105 if (MI->getOperand(OpNo).isImm()) {
106 O << "$+" << MI->getOperand(OpNo).getImm()*4;
108 printOp(MI->getOperand(OpNo), O);
122 if (MI->getOperand(OpNo).isImm())
[all...] |
| HexagonPeephole.cpp | 131 MachineOperand &Dst = MI->getOperand(0);
132 MachineOperand &Src = MI->getOperand(1);
152 MachineOperand &Dst = MI->getOperand(0);
153 MachineOperand &Src1 = MI->getOperand(1);
154 MachineOperand &Src2 = MI->getOperand(2);
167 MachineOperand &Dst = MI->getOperand(0);
168 MachineOperand &Src = MI->getOperand(1);
185 MachineOperand &Dst = MI->getOperand(0);
186 MachineOperand &Src = MI->getOperand(1);
224 MachineOperand &Op0 = MI->getOperand(0)
[all...] |
| HexagonNewValueJump.cpp | 131 if (II->getOperand(i).isReg() &&
132 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
135 unsigned Reg = II->getOperand(i).getReg();
210 int64_t v = MI->getOperand(2).getImm();
224 cmpReg1 = MI->getOperand(1).getReg();
227 cmpOp2 = MI->getOperand(2).getReg();
406 predReg = MI->getOperand(0).getReg();
411 // if(!jmpInstr->getOperand(0).isKill()) break;
435 jmpTarget = MI->getOperand(1).getMBB()
[all...] |
| HexagonRegisterInfo.cpp | 128 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
148 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
150 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
171 getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
172 MI.getOperand(0).getReg();
187 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
188 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
215 MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
216 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
221 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister()
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 34 assert(MI->getNumOperands() == 4 && MI->getOperand(0).isReg()
35 && MI->getOperand(1).isImm() && "unexpected custom DBG_VALUE");
36 return MachineLocation(MI->getOperand(0).getReg(),
37 MI->getOperand(1).getImm());
161 const MachineOperand &MO = MI->getOperand(OpNum);
195 if (!MI->getOperand(OpNum).isImm())
197 O << MI->getOperand(OpNum).getImm();
202 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
207 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
225 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI
[all...] |
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 34 unsigned char SH = MI->getOperand(2).getImm();
35 unsigned char MB = MI->getOperand(3).getImm();
36 unsigned char ME = MI->getOperand(4).getImm();
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
67 unsigned char SH = MI->getOperand(2).getImm();
68 unsigned char ME = MI->getOperand(3).getImm();
89 unsigned Code = MI->getOperand(OpNo).getImm();
91 unsigned CCReg = MI->getOperand(OpNo+1).getReg();
139 int Value = MI->getOperand(OpNo).getImm()
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 81 switch (MI->getOperand(0).getImm()) {
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
126 const MCOperand &Dst = MI->getOperand(0);
127 const MCOperand &MO1 = MI->getOperand(1);
128 const MCOperand &MO2 = MI->getOperand(2);
155 MI->getOperand(0).getReg() == ARM::SP &&
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
92 Base = Addr.getOperand(0);
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
99 Base = Addr.getOperand(1);
100 Offset = Addr.getOperand(0).getOperand(0);
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
104 Base = Addr.getOperand(0);
105 Offset = Addr.getOperand(1).getOperand(0)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 40 isa<ConstantInt>(I->getOperand(2)))
46 (CheapToScalarize(BO->getOperand(0), isConstant) ||
47 CheapToScalarize(BO->getOperand(1), isConstant)))
51 (CheapToScalarize(CI->getOperand(0), isConstant) ||
52 CheapToScalarize(CI->getOperand(1), isConstant)))
73 if (!isa<ConstantInt>(III->getOperand(2)))
75 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue();
80 return III->getOperand(1);
84 return FindScalarElement(III->getOperand(0), EltNo);
88 unsigned LHSWidth = SVI->getOperand(0)->getType()->getVectorNumElements()
[all...] |
| InstCombineSelect.cpp | 32 LHS = ICI->getOperand(0);
33 RHS = ICI->getOperand(1);
36 if (SI->getTrueValue() == ICI->getOperand(0) &&
37 SI->getFalseValue() == ICI->getOperand(1)) {
52 if (SI->getTrueValue() == ICI->getOperand(1) &&
53 SI->getFalseValue() == ICI->getOperand(0)) {
130 if (TI->getOperand(0)->getType() != FI->getOperand(0)->getType())
136 FI->getOperand(0)->getType()->getVectorNumElements())
143 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0)
[all...] |
| InstCombineCasts.cpp | 43 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
48 return I->getOperand(0);
55 return I->getOperand(0);
63 DecomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset);
118 DecomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset);
186 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned);
187 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned);
197 if (I->getOperand(0)->getType() == Ty)
198 return I->getOperand(0);
202 Res = CastInst::CreateIntegerCast(I->getOperand(0), Ty
[all...] |
| InstCombineShifts.cpp | 23 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType());
24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
92 if (MaskedValueIsZero(I->getOperand(0),
95 return CanEvaluateTruncated(I->getOperand(0), Ty);
112 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) &&
113 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC);
117 CI = dyn_cast<ConstantInt>(I->getOperand(1));
132 if (MaskedValueIsZero(I->getOperand(0)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 112 MI->getOperand(0).getReg(),
113 MI->getOperand(1).getReg());
121 MI->getOperand(0).getReg(),
122 MI->getOperand(1).getReg());
130 MI->getOperand(0).getReg(),
131 MI->getOperand(1).getReg());
137 unsigned maskedRegister = MI->getOperand(0).getReg();
145 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
146 MI->getOperand(1).getFPImm()->getValueAPF()
150 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg()
[all...] |
| R600ExpandSpecialInstrs.cpp | 74 uint64_t Flags = MI.getOperand(3).getImm();
78 MI.getOperand(2).getImm(), // opcode
79 MI.getOperand(0).getReg(), // dst
80 MI.getOperand(1).getReg(), // src0
110 MI.getOperand(2).getImm());
116 DstReg = MI.getOperand(Chan).getReg();
121 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
139 MI.getOperand(2).getImm());
147 DstReg = MI.getOperand(Chan-2).getReg();
150 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg)
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
|
| /external/llvm/include/llvm/Support/ |
| GetElementPtrTypeIterator.h | 59 return CT->getTypeAtIndex(getOperand());
66 Value *getOperand() const { return *OpIt; }
70 CurTy = CT->getTypeAtIndex(getOperand());
87 (GEP->getOperand(0)->getType()->getScalarType(), GEP->op_begin()+1);
94 (GEP.getOperand(0)->getType()->getScalarType(), GEP.op_begin()+1);
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 36 const MCOperand &Op = MI->getOperand(OpNo);
48 const MCOperand &Op = MI->getOperand(OpNo);
62 const MCOperand &Base = MI->getOperand(OpNo);
63 const MCOperand &Disp = MI->getOperand(OpNo+1);
90 unsigned CC = MI->getOperand(OpNo).getImm();
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 55 const MCOperand &MOImm = MI->getOperand(OpNum);
65 unsigned ExtImm = MI->getOperand(OpNum).getImm();
94 const MCOperand &Imm12Op = MI->getOperand(OpNum);
118 const MCOperand &MO = MI->getOperand(OpNum);
125 const MCOperand &ImmROp = MI->getOperand(OpNum);
133 const MCOperand &ImmSOp = MI->getOperand(OpNum);
142 const MCOperand &ImmSOp = MI->getOperand(OpNum);
143 const MCOperand &ImmROp = MI->getOperand(OpNum - 1);
156 const MCOperand &CRx = MI->getOperand(OpNum);
165 const MCOperand &ScaleOp = MI->getOperand(OpNum)
[all...] |
