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  /external/llvm/include/llvm/Target/
TargetFrameLowering.h 32 /// spill locations) can be stored.
98 /// allowed to spill it anywhere it chooses.
127 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
  /external/llvm/lib/CodeGen/
RegAllocFast.cpp 75 bool Dirty; // Register needs spill.
207 // Allocate a new stack object for this spill location...
282 // instruction, not on the spill.
317 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
330 /// spillAll - Spill all dirty virtregs without killing them.
527 // Ignore the hint if we would have to spill a dirty register.
713 // we must spill and reallocate.
861 // Modify DBG_VALUE now that the value is in a spill slot.
868 DEBUG(dbgs() << "Modifying debug info due to spill:" <<
    [all...]
LiveStackAnalysis.cpp 59 assert(Slot >= 0 && "Spill slot indice must be >= 0");
RegAllocPBQP.cpp 14 // register assignment. If any variables are selected for spilling then spill
367 ++pregOpt; // +1 to account for spill option.
495 spiller->spill(LRE);
504 assert(!(*itr)->empty() && "Empty spill range.");
511 // We need another round if spill intervals were added.
564 // * Spill if necessary
SplitKit.h 225 /// it to overlap the other intervals. If it is going to spill anyway, no
257 /// The current spill mode, selected by reset().
290 /// LiveRangeCalc instance for the complement interval when in spill mode.
293 /// getLRCalc - Return the LRCalc to use for RegIdx. In spill mode, the
295 /// LRCalc instance. When not in spill mode, all intervals can share one.
331 /// way that minimizes code size. This implements the SM_Size spill mode.
  /external/llvm/lib/Target/PowerPC/
PPCFrameLowering.cpp 56 /// the spill instruction refers to an undefined register. This code needs
221 // SVR4, we also require a stack frame if we need to spill the CR,
222 // since this spill area is addressed relative to the stack pointer.
545 // For SVR4, don't emit a move for the CR spill slot if we haven't
552 // For 64-bit SVR4 when we have spilled CRs, the spill location
830 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
    [all...]
  /dalvik/vm/mterp/x86/
OP_EXECUTE_INLINE.S 17 SPILL(rIBASE) # preserve rIBASE
OP_INSTANCE_OF.S 21 SPILL(rIBASE) # preserve rIBASE
OP_NEW_INSTANCE.S 16 SPILL(rIBASE)
  /external/libffi/src/ia64/
ffi.c 43 specific format used by ldf.fill/stf.spill. All we care about is
73 /* Store VALUE to ADDR in the current cpu implementation's fp spill format.
79 asm ("stf.spill %0 = %1%P0" : "=m" (*addr) : "f"(value));
82 fp spill format. As above, this must also be a macro. */
  /external/llvm/include/llvm/CodeGen/PBQP/Heuristics/
Briggs.h 14 // then the node with the minimal spill-cost to degree ratio is removed.
32 /// problem represent storage options, with the first being the spill
40 /// the lowest estimated spill cost is selected and push to the solver stack
122 /// exception. Nodes whose spill cost (element 0 of their cost vector) is
  /external/llvm/lib/Target/ARM/
Thumb1FrameLowering.cpp 102 // Determine the sizes of each callee-save spill areas and record which frame
103 // belongs to which callee-save spill areas.
158 // Determine starting offsets of spill areas.
270 // Move SP to start of FP callee save spill area.
Thumb1RegisterInfo.cpp 472 // If this is a thumb spill / restore, we will be using a constpool load to
503 /// saveScavengerRegister - Spill the register so it can be used by the
511 // Thumb1 can't use the emergency spill slot on the stack because
588 // means the stack pointer cannot be used to access the emergency spill slot
593 "Cannot use SP to access the emergency spill slot in "
596 "Cannot use SP to access the emergency spill slot in "
  /external/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 124 // Insert instructions that spill eh data registers.
225 // It's killed at the spill, unless the register is RA and return address
233 // Insert the spill to the stack frame.
283 // Create spill slots for eh data registers if function calls eh_return.
  /external/llvm/test/CodeGen/ARM/
crash-O0.ll 7 ; This function would crash RegAllocFast because it tried to spill %CPSR.
  /external/v8/src/ia32/
lithium-gap-resolver-ia32.h 103 // If we had to spill on demand, the currently spilled register's
  /external/webkit/Source/WebCore/rendering/style/
StyleRareNonInheritedData.h 100 bool textOverflow : 1; // Whether or not lines that spill out should be truncated with "..."
  /prebuilts/gcc/darwin-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/
emit-rtl.h 41 /* Set the attributes for MEM appropriate for a spill slot. */
  /prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/
emit-rtl.h 41 /* Set the attributes for MEM appropriate for a spill slot. */
  /prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/
emit-rtl.h 41 /* Set the attributes for MEM appropriate for a spill slot. */
  /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/
emit-rtl.h 41 /* Set the attributes for MEM appropriate for a spill slot. */
  /external/llvm/docs/CommandGuide/
lli.rst 187 **-disable-spill-fusing**
189 Disable fusing of spill code into instructions.
  /external/llvm/include/llvm/CodeGen/
LiveRangeEdit.h 1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
197 /// as currently those new intervals are not guaranteed to spill.
  /external/llvm/test/CodeGen/X86/
pr1505b.ll 40 ; Spill returned value:
48 ; Spill returned value:
  /external/valgrind/main/docs/internals/
register-uses.txt 80 r30 y altivec spill temporary
190 r30 y altivec spill temporary

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