| /external/llvm/test/CodeGen/X86/ |
| sse-intel-ocl.ll | 73 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
74 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
75 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
76 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
77 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
78 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
79 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
80 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
|
| avx-intel-ocl.ll | 68 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
69 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
70 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
71 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
72 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
73 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
74 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
75 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
76 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
77 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rsp).*}} # 32-byte Spill
[all...] |
| /external/libffi/src/ia64/ |
| unix.S | 304 /* Spill all of the possible argument registers. */
308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 1
[all...] |
| /dalvik/vm/mterp/x86/ |
| OP_MONITOR_EXIT.S | 19 SPILL(rIBASE)
|
| bindiv.S | 12 SPILL(rIBASE)
|
| bindiv2addr.S | 8 SPILL(rIBASE)
|
| bindivLit8.S | 9 SPILL(rIBASE)
|
| OP_SGET.S | 42 SPILL(rIBASE)
49 SPILL(rIBASE)
|
| OP_SGET_WIDE.S | 43 SPILL(rIBASE)
50 SPILL(rIBASE)
|
| OP_SPUT.S | 42 SPILL(rIBASE)
49 SPILL(rIBASE)
|
| OP_SPUT_OBJECT.S | 46 SPILL(rIBASE)
53 SPILL(rIBASE)
|
| OP_SPUT_WIDE.S | 44 SPILL(rIBASE)
51 SPILL(rIBASE)
|
| OP_INVOKE_STATIC.S | 35 SPILL(rIBASE)
56 SPILL(rIBASE)
|
| OP_CONST_CLASS.S | 29 SPILL(rIBASE)
|
| OP_CONST_STRING.S | 28 SPILL(rIBASE)
|
| /external/llvm/test/CodeGen/AArch64/ |
| tls-dynamic-together.ll | 4 ; glue) then LLVM will separate them quite happily (with a spill at O0, hence
|
| /external/llvm/test/CodeGen/PowerPC/ |
| vrspill.ll | 4 ; This verifies that we generate correct spill/reload code for vector regs.
|
| /external/llvm/lib/CodeGen/ |
| Spiller.cpp | 72 /// Add spill ranges for every use/def of the live interval, inserting loads
81 "Attempting to spill already spilled value.");
84 "Trying to spill a stack slot.");
86 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
167 /// Spills any live range using the spill-everywhere method with no attempt at
176 void spill(LiveRangeEdit &LRE) { function in class:__anon11494::TrivialSpiller
|
| StackSlotColoring.cpp | 53 // SSIntervals - Spill slot intervals.
56 // SSRefs - Keep a list of frame index references for each spill slot.
65 // AllColors - If index is set, it's a spill slot, i.e. color.
66 // FIXME: This assumes PEI locate spill slot with smaller indices
133 /// ScanForSpillSlotRefs - Scan all the machine instructions for spill slot
134 /// references and update spill slot weights.
164 /// InitializeSlots - Process all spill stack slot liveintervals and add them
174 // Gather all spill slots into a list.
175 DEBUG(dbgs() << "Spill slot intervals:\n");
230 assert(NextColor != -1 && "No more spill slots?")
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_generic_reg_alloc2.c | 51 providing we can arrange for the dst to have the same spill slot.
66 /* The "home" spill slot, if needed. Never changes. */
103 spill. */
106 rreg has the same value as the spill slot for the associated
108 spill store or reload for this rreg. */
164 sequence. Point is to select a virtual register to spill, by
170 caller to arbitrarily restrict the set of spill candidates to be
174 spill, or -1 if none was found. */
207 /* Check that this vreg has been assigned a sane spill offset. */
327 /* Return one, or, if we're unlucky, two insn(s) to spill/restore
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| aligned-spill.ll | 7 ; This function is forced to spill a double.
8 ; Verify that the spill slot is properly aligned.
33 ; Since the spill slot is only 8 bytes, technically it would be fine to only
47 ; Spill 7 d-registers.
71 ; Spill 7 d-registers, leave a hole.
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveStackAnalysis.h | 60 assert(Slot >= 0 && "Spill slot indice must be >= 0");
67 assert(Slot >= 0 && "Spill slot indice must be >= 0");
78 assert(Slot >= 0 && "Spill slot indice must be >= 0");
|
| /external/llvm/lib/Target/X86/ |
| X86CompilationCallback_Win64.asm | 24 ; WARNING: We cannot use register spill area - we're generating stubs by hands!
33 ; Save all XMM arg registers. Also allocate reg spill area.
|
| /external/llvm/test/CodeGen/ARM/ |
| 2010-05-18-LocalAllocCrash.ll | 3 ;; This test would spill %R4 before the call to zz, but it forgot to move the
4 ; 'last use' marker to the spill.
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 95 // Integer spill area is handled with "pop".
150 // Determine the sizes of each callee-save spill areas and record which frame
151 // belongs to which callee-save spill areas.
216 // For iOS, FP is R7, which has now been stored in spill area 1.
218 // into spill area 1, including the FP in R11. In either case, it is
233 // Determine starting offsets of spill areas.
383 // Move SP to start of FP callee save spill area.
539 // since it's available. This is handy for the emergency spill slot, in
725 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
727 /// pointer pointing to the d8 spill slot
[all...] |
