| /external/kernel-headers/original/asm-arm/ |
| domain.h | 26 * supersections to reduce TLB misses and footprint.
|
| /external/oprofile/events/arm/armv7-ca9/ |
| events | 31 event:0x82 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_TLB : Number of cycles where CPU is stalled because of main TLB misses on requests issued by the instruction side
32 event:0x83 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_TLB : Number of cycles where CPU is stalled because of main TLB misses on requests issued by the data side
33 event:0x84 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_UTLB : Number of cycles where CPU is stalled because of micro TLB misses on the instruction side
34 event:0x85 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_ULTB : Number of cycles where CPU is stalled because of micro TLB misses on the data side
|
| /external/oprofile/events/x86-64/family12h/ |
| events | 16 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
|
| /external/oprofile/events/x86-64/family14h/ |
| events | 16 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
|
| /external/webkit/LayoutTests/fast/xpath/ |
| preceding-axis.xhtml | 5 <title>XPath preceding axis misses nested elements</title>
|
| /external/oprofile/events/ppc64/970/ |
| events | 30 event:0X022 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
40 event:0X032 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses
174 event:0X106 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load misses
175 event:0X107 counters:7 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load misses
184 event:0X116 counters:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP17 : (Group 17 pm_lsu_store1) L1 D cache store misses
198 event:0X130 counters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU0 DERAT misses
199 event:0X131 counters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU1 DERAT misses
228 event:0X160 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Data TLB misses
229 event:0X161 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Instruction TLB misses
230 event:0X162 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load misses
[all...] |
| /dalvik/vm/ |
| AtomicCache.cpp | 132 pCache->misses++;
177 pCache->misses, pCache->fills,
180 (pCache->fail + pCache->hits + pCache->misses + pCache->fills),
|
| /external/oprofile/events/mips/25K/ |
| events | 35 event:0x11 counters:0,1 um:zero minimum:500 name:UTLB_MISSES : U-TLB misses
36 event:0x12 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_IFETCH : Raw count of Joint-TLB misses for instruction fetch
37 event:0x13 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_LOADS_STORES : Raw count of Joint-TLB misses for loads/stores
|
| /external/oprofile/events/mips/r10000/ |
| events | 23 event:0x09 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
25 event:0x0a counters:0 um:zero minimum:500 name:SCACHE_MISSES_INSTRUCTION : Secondary cache misses (instruction)
26 event:0x0a counters:1 um:zero minimum:500 name:SCACHE_MISSES_DATA : Secondary cache misses (data)
|
| /frameworks/base/core/java/android/database/sqlite/ |
| SQLiteDebug.java | 133 /** statement cache stats: hits/misses/cachesize */
137 int hits, int misses, int cachesize) {
142 this.cache = hits + "/" + misses + "/" + cachesize;
|
| /external/oprofile/events/ppc64/power6/ |
| events | 310 event:0X0302 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache store misses
311 event:0X0303 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache load misses
[all...] |
| /external/oprofile/events/i386/core_2/ |
| unit_masks | 64 0x02 MISS_LD DTLB misses due to load operations.
65 0x04 L0_MISS_LD L0 DTLB misses due to load operations.
66 0x08 MISS_ST TLB misses due to store operations.
126 0x02 ITLB small page misses
127 0x10 ITLB large page misses
|
| /external/oprofile/events/mips/24K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
66 event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
89 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
90 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
91 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
92 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
93 event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
|
| /external/chromium/chrome/browser/safe_browsing/ |
| filter_false_positive_perftest.cc | 211 // false positive rate (misses) against a URL list.
226 int misses = 0; local
265 ++misses;
280 << ", misses: " << misses; local
283 << ", weighted misses: " << weighted_misses;
|
| /external/oprofile/events/x86-64/family11h/ |
| events | 39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
44 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
45 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
51 event:0x4c counters:0,1,2,3 um:dcachemisslocked minimum:500 name:DCACHE_MISS_LOCKED_INSTRUCTIONS : DCACHE misses by locked instructions
60 event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
65 event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
|
| /external/oprofile/events/x86-64/hammer/ |
| events | 39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
44 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
45 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
51 event:0x4c counters:0,1,2,3 um:dcachemisslocked minimum:500 name:DCACHE_MISS_LOCKED_INSTRUCTIONS : DCACHE misses by locked instructions
60 event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
65 event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
|
| /dalvik/vm/compiler/ |
| Ralloc.cpp | 23 * code generation will handle misses. It might be worthwhile to collaborate
|
| /external/webrtc/src/system_wrappers/source/spreadsortlib/ |
| constants.hpp | 31 //This should be tuned to your processor cache; if you go too large you get cache misses on bins
|
| /frameworks/base/tools/aapt/ |
| ResourceIdCache.cpp | 103 printf("Misses: %ld\n", mMisses);
|
| /external/oprofile/events/ppc64/power4/ |
| events | 30 event:0X022 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
40 event:0X032 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses
98 event:0X090 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP9 : (Group 9 pm_xlate1) Instruction TLB misses
99 event:0X091 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP9 : (Group 9 pm_xlate1) Data TLB misses
103 event:0X095 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP9 : (Group 9 pm_xlate1) DERAT misses
108 event:0X0A0 counters:0 um:zero minimum:1000 name:PM_ISLB_MISS_GRP10 : (Group 10 pm_xlate2) Instruction SLB misses
109 event:0X0A1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP10 : (Group 10 pm_xlate2) Data SLB misses
113 event:0X0A5 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP10 : (Group 10 pm_xlate2) DERAT misses
119 event:0X0B1 counters:1 um:zero minimum:1000 name:PM_L3B0_DIR_MIS_GRP11 : (Group 11 pm_gps1) L3 bank 0 directory misses
123 event:0X0B5 counters:5 um:zero minimum:1000 name:PM_L3B1_DIR_MIS_GRP11 : (Group 11 pm_gps1) L3 bank 1 directory misses
[all...] |
| /external/oprofile/events/alpha/ev5/ |
| events | 27 event:0x13 counters:2 um:zero minimum:256 name:ICACHE_MISSES : Instruction cache misses
29 event:0x15 counters:2 um:zero minimum:256 name:DCACHE_MISSES : Data cache misses
|
| /external/oprofile/events/mips/74K/ |
| events | 47 event:0x1d counters:0,2 um:zero minimum:500 name:L2_CACHE_MISSES : 29-0 L2 Cache Misses
98 event:0x404 counters:1,3 um:zero minimum:500 name:ITLB_MISSES : 4-1 Instruction micro-TLB misses
99 event:0x405 counters:1,3 um:zero minimum:500 name:JTLB_INSN_MISSES : 5-1 Joint TLB instruction misses
100 event:0x406 counters:1,3 um:zero minimum:500 name:ICACHE_MISSES : 6-1 Instruction cache misses, includes misses from fetch-ahead and speculation
118 event:0x418 counters:1,3 um:zero minimum:500 name:DCACHE_MISSES : 24-1 Data cache misses
119 event:0x419 counters:1,3 um:zero minimum:500 name:JTLB_DATA_MISSES : 25-1 Joint TLB data (non-instruction) misses
121 event:0x41b counters:1,3 um:zero minimum:500 name:LOAD_STORE_NO_FILL_REQUESTS : 27-1 Load/store graduations not resulting in a bus request because misses at integer pipe graduation turn into hit or merge with outstanding fill request
|
| /external/oprofile/events/ppc/7450/ |
| events | 16 event:0x12 counters:2 um:zero minimum:3000 name:DTLB_MISSES : DTLB misses
18 event:0x15 counters:0,1 um:zero minimum:3000 name:L1_ICACHE_MISSES : L1 Instruction Cache Misses
|
| /external/oprofile/events/x86-64/family10/ |
| events | 54 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
66 event:0x4c counters:0,1,2,3 um:locked_instruction_dcache_miss minimum:500 name:LOCKED_INSTRUCTIONS_DCACHE_MISSES : The number of dta cache misses by locked instructions.
78 event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
84 event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
169 event:0x4e1 counters:0,1,2,3 um:l3_cache minimum:500 name:L3_CACHE_MISSES : Number of L3 cache misses from each core
183 event:0xf006 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_L1_ITLB_MISSES_L2_ITLB_HITS : IBS L1 ITLB misses (and L2 ITLB hits)
185 event:0xf008 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ICACHE_MISSES : IBS Instruction cache misses
209 event:0xf204 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_MISS_L2_DTLB_HIT : IBS L1 DTLB misses L2 hits
210 event:0xf205 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_L2_DTLB_MISS : IBS L1 and L2 DTLB misses
211 event:0xf206 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DATA_CACHE_MISS : IBS data cache misses
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
72 event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
104 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
105 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
106 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
107 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
108 event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
|
