| /external/oprofile/events/mips/r12000/ |
| unit_masks | 6 name:zero type:mandatory default:0x0
|
| /external/oprofile/events/mips/34K/ |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesse
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| subreg-to-reg-0.ll | 3 ; Do eliminate the zero-extension instruction and rely on
4 ; x86-64's implicit zero-extension!
|
| /external/llvm/test/MC/ELF/ |
| org.s | 3 .zero 4
5 .zero 4
|
| pic-diff.s | 22 .zero 4
25 .zero 1
28 .zero 8
|
| /external/srec/doc/logs/srec/ |
| out_SHIP_change_sample_rate2.txt | 15 C: oh eight four zero nine two five one eight five
21 TRANSCRIPTION : 'oh eight four zero nine two five one eight five'
137 C: zero seven six five nine oh zero two five two
143 TRANSCRIPTION : 'zero seven six five nine oh zero two five two'
144 LITERAL[ 0] : 'zero seven six five nine oh zero two five two'
149 LITERAL[ 1] : 'zero seven seven five nine oh zero two five two
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| o32_cc.ll | 51 ; CHECK: addiu $4, $zero, 12
52 ; CHECK: addiu $5, $zero, 13
53 ; CHECK: addiu $6, $zero, 14
54 ; CHECK: addiu $7, $zero, 15
67 ; CHECK: addiu $6, $zero, 23
78 ; CHECK: addiu $6, $zero, 33
79 ; CHECK: addiu $7, $zero, 24
90 ; CHECK: addiu $5, $zero, 43
91 ; CHECK: addiu $6, $zero, 34
103 ; CHECK: addiu $4, $zero, 2
[all...] |
| imm.ll | 22 ; CHECK: addiu ${{[0-9]+}}, $zero, 4660
29 ; CHECK: addiu ${{[0-9]+}}, $zero, -32204
36 ; CHECK: ori ${{[0-9]+}}, $zero, 33332
|
| divrem.ll | 3 ; CHECK: div $zero,
10 ; CHECK: div $zero,
17 ; CHECK: divu $zero,
24 ; CHECK: divu $zero,
31 ; CHECK: div $zero,
40 ; CHECK: divu $zero,
|
| /external/compiler-rt/lib/ubsan/lit_tests/Integer/ |
| div-zero.cpp | 1 // RUN: %clang -fsanitize=integer-divide-by-zero -DDIVIDEND=0 %s -o %t && %t 2>&1 | FileCheck %s
2 // RUN: %clang -fsanitize=integer-divide-by-zero -DDIVIDEND=1U %s -o %t && %t 2>&1 | FileCheck %s
3 // RUN: %clang -fsanitize=float-divide-by-zero -DDIVIDEND=1.5 %s -o %t && %t 2>&1 | FileCheck %s
4 // RUN: %clang -fsanitize=integer-divide-by-zero -DDIVIDEND='intmax(123)' %s -o %t && %t 2>&1 | FileCheck %s
13 // CHECK: div-zero.cpp:[[@LINE+1]]:12: runtime error: division by zero
|
| /libcore/luni/src/test/java/libcore/java/lang/ |
| OldAndroidEnumTest.java | 26 ZERO, ONE, TWO, THREE, FOUR {boolean isFour() {
40 assertTrue(MyEnum.ZERO.compareTo(MyEnum.ONE) < 0);
41 assertEquals(MyEnum.ZERO, MyEnum.ZERO);
53 e = MyEnum.ZERO;
56 case ZERO:
|
| /external/oprofile/events/ppc64/power7/ |
| events | 15 event:0X001 counters:0 um:zero minimum:10000 name:CYCLES : Processor Cycles
18 event:0X002 counters:3 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
22 event:0X0010 counters:0 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor Cycles
23 event:0X0011 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
24 event:0X0012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Number of PowerPC instructions successfully dispatched.
25 event:0X0013 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_utilization) Number of PowerPC Instructions that completed.
26 event:0X0014 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP1 : (Group 1 pm_utilization) Number of run instructions completed.
27 event:0X0015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
30 event:0X0020 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP2 : (Group 2 pm_branch1) The count value of a Branch and Count instruction was predicted
31 event:0X0021 counters:1 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP2 : (Group 2 pm_branch1) The target address of a Branch to (…)
[all...] |
| /external/libpng/contrib/pngsuite/ |
| README | 41 Testing basn0g01.png: PASS (524 zero samples)
43 Testing basn0g02.png: PASS (448 zero samples)
45 Testing basn0g04.png: PASS (520 zero samples)
47 Testing basn0g08.png: PASS (3 zero samples)
50 Testing basn0g16.png: PASS (1 zero samples)
53 Testing basn2c08.png: PASS (6 zero samples)
56 Testing basn2c16.png: PASS (592 zero samples)
59 Testing basn3p01.png: PASS (512 zero samples)
61 Testing basn3p02.png: PASS (448 zero samples)
63 Testing basn3p04.png: PASS (544 zero samples
[all...] |
| /external/v8/test/mjsunit/ |
| smi-negative-zero.js | 30 var zero = 0; variable
40 assertEquals(-Infinity, one / (-zero), "one / -0 I");
42 assertEquals(-Infinity, one / (zero * minus_one), "one / -1");
43 assertEquals(-Infinity, one / (minus_one * zero), "one / -0 II");
44 assertEquals(Infinity, one / (zero * zero), "one / 0 I");
47 assertEquals(-Infinity, one / (zero / minus_one), "one / -0 III");
48 assertEquals(Infinity, one / (zero / one), "one / 0 II");
58 assertEquals(-Infinity, one / (-1 * zero), "bar2");
59 assertEquals(Infinity, one / (0 * zero), "bar3")
[all...] |
| /external/icu4c/test/intltest/ |
| itrbnf.cpp | 245 errln("Number of rule set names should be more than zero");
779 // small and large values, positive, &NEGative, zero
782 const llong ZERO;
806 &ZERO, &ONE, &NEG_ONE, &THREE, &NEG_THREE, &TWO_TO_16, &NEG_TWO_TO_16, &TWO_TO_32, &NEG_TWO_TO_32
810 &ZERO, &ZERO, &ZERO, &ZERO, &ZERO, &ZERO, &ZERO, &ZERO, &ZERO
[all...] |
| /external/oprofile/events/i386/pii/ |
| events | 3 event:0x79 counters:0,1 um:zero minimum:6000 name:CPU_CLK_UNHALTED : clocks processor is not halted
4 event:0x43 counters:0,1 um:zero minimum:500 name:DATA_MEM_REFS : all memory references, cachable and non
5 event:0x45 counters:0,1 um:zero minimum:500 name:DCU_LINES_IN : total lines allocated in the DCU
6 event:0x46 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_IN : number of M state lines allocated in DCU
7 event:0x47 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_OUT : number of M lines evicted from the DCU
8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
9 event:0x80 counters:0,1 um:zero minimum:500 name:IFU_IFETCH : number of non/cachable instruction fetches
10 event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
11 event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalle
[all...] |
| /external/oprofile/events/x86-64/hammer/ |
| events | 23 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
24 event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
28 event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
29 event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
30 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
34 event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH_INSTRUCTIONS : Retired CLFLUSH instructions
35 event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID_INSTRUCTIONS : Retired CPUID instructions
38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
44 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hit
[all...] |
| /external/oprofile/events/x86-64/family12h/ |
| events | 15 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
16 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
19 event:0x76 counters:0,1,2,3 um:zero minimum:50000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
20 event:0xc0 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
21 event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
22 event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
23 event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired mispredicted branch instructions
|
| /external/oprofile/events/x86-64/family14h/ |
| events | 15 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
16 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
19 event:0x76 counters:0,1,2,3 um:zero minimum:50000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
20 event:0xc0 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
21 event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
22 event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
23 event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired mispredicted branch instructions
|
| /external/oprofile/events/x86-64/family11h/ |
| events | 25 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles in which the FPU is empty
26 event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
30 event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
31 event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
32 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
39 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
44 event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
45 event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
46 event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned Accesse
[all...] |
| /external/oprofile/events/i386/piii/ |
| events | 3 event:0x79 counters:0,1 um:zero minimum:6000 name:CPU_CLK_UNHALTED : clocks processor is not halted
4 event:0x43 counters:0,1 um:zero minimum:500 name:DATA_MEM_REFS : all memory references, cachable and non
5 event:0x45 counters:0,1 um:zero minimum:500 name:DCU_LINES_IN : total lines allocated in the DCU
6 event:0x46 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_IN : number of M state lines allocated in DCU
7 event:0x47 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_OUT : number of M lines evicted from the DCU
8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
9 event:0x80 counters:0,1 um:zero minimum:500 name:IFU_IFETCH : number of non/cachable instruction fetches
10 event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
11 event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalle
[all...] |
| /external/e2fsprogs/tests/f_recnect_bad/ |
| expect.1 | 3 i_faddr for inode 15 (/test/quux) is 23, should be zero.
6 i_dir_acl for inode 15 (/test/quux) is 12, should be zero.
9 i_file_acl for inode 13 (/test/???) is 12, should be zero.
12 i_faddr for inode 13 (/test/???) is 12, should be zero.
22 i_file_acl for inode 28 (...) is 4294967295, should be zero.
|
| /external/libxml2/ |
| trionan.h | 51 * Return negative zero.
56 * If number is a NaN return non-zero, otherwise return zero.
67 * If number is finite return non-zero, otherwise return zero.
|
| /external/clang/test/CodeGen/ |
| 2008-01-25-ZeroSizedAggregate.c | 4 // Aggregates of size zero should be dropped from argument list.
16 // Proper handling of zero sized fields during type conversion.
32 // Taking address of a zero sized field.
|
| /external/srec/tools/thirdparty/OpenFst/fst/lib/ |
| random-weight.h | 32 // The boolean 'allow_zero' below determines whether Zero() and zero
49 return Weight::Zero();
58 bool allow_zero_; // permit Zero() and zero divisors
76 return Weight::Zero();
85 bool allow_zero_; // permit Zero() and zero divisors
90 // strings chosen from {1,...,kAlphabetSize}^{0,kMaxStringLength} U { Zero }
104 return Weight::Zero();
[all...] |
