| /external/llvm/lib/Target/X86/ |
| X86PadShortFunction.cpp | 209 BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP));
210 BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP));
|
| X86InstrInfo.cpp | [all...] |
| X86VZeroUpper.cpp | 264 BuildMI(BB, I, dl, TII->get(X86::VZEROUPPER));
|
| X86FloatingPoint.cpp | 252 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
261 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
844 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.cpp | 115 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
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| MipsISelLowering.cpp | [all...] |
| MipsCodeEmitter.cpp | 305 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO)
309 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::JALR), Mips::RA)
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 173 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
185 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
201 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
212 MemMI = BuildMI(MF, MI->getDebugLoc(),
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 MemMI = BuildMI(MF, MI->getDebugLoc(),
227 MemMI = BuildMI(MF, MI->getDebugLoc(),
419 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0)
[all...] |
| A15SDOptimizer.cpp | 437 AddDefaultPred(BuildMI(MBB,
456 BuildMI(MBB,
472 BuildMI(MBB,
491 AddDefaultPred(BuildMI(MBB,
507 BuildMI(MBB,
523 BuildMI(MBB,
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| ARMISelLowering.cpp | [all...] |
| ARMConstantIslandPass.cpp | 545 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
[all...] |
| ARMInstrInfo.cpp | 125 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
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| ARMLoadStoreOptimizer.cpp | 338 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
280 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
322 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
443 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
492 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
508 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
541 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
579 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
597 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
647 MachineInstrBuilder MIB = BuildMI(*MF, DL, II)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 691 BuildMI(*Preheader, InsertPos, dl,
696 BuildMI(*Preheader, InsertPos, dl,
710 BuildMI(*Preheader, InsertPos, dl,
715 BuildMI(*Preheader, InsertPos, dl,
719 BuildMI(*Preheader, InsertPos, dl,
726 BuildMI(*Preheader, InsertPos, dl,
756 BuildMI(*LastMBB, LastI, dl,
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| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 145 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
148 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
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| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 114 BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::NOP));
121 BuildMI(MBB, ++J, I->getDebugLoc(),
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| FPMover.cpp | 120 MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 792 BuildMI(*PH, InsertPos, DL, SubD, SubR);
818 BuildMI(*PH, InsertPos, DL, AddD, AddR)
839 BuildMI(*PH, InsertPos, DL, LsrD, LsrR)
[all...] |
| HexagonInstrInfo.cpp | 153 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
155 BuildMI(&MBB, DL,
161 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
162 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
395 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
399 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
404 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
413 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
417 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
419 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 165 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
176 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
181 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
186 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
201 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
206 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
211 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
223 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
229 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
235 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64BranchFixupPass.cpp | 376 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::Bimm)).addMBB(NewBB);
512 InvertedMI = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(InvertedOpcode));
588 BuildMI(MBB, DebugLoc(), TII->get(AArch64::Bimm))
|
| /external/llvm/lib/CodeGen/ |
| PHIElimination.cpp | 243 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
259 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
383 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
392 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
|
