| /external/llvm/lib/Target/R600/ |
| SIISelLowering.h | 44 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| R600ISelLowering.h | 38 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 150 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
166 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
258 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
260 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
268 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
| X86FastISel.cpp | 90 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
325 /// ISD::SIGN_EXTEND).
326 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
746 SmallVector<ISD::OutputArg, 4> Outs;
797 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
798 ISD::SIGN_EXTEND;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 56 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
57 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
58 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
59 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
60 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
61 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
62 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
63 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
64 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
65 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 113 if (User->getOpcode() == ISD::CopyToReg &&
196 if (User->getOpcode() == ISD::CopyToReg &&
233 if (User->getOpcode() == ISD::CopyToReg &&
336 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
461 if (User->getOpcode() == ISD::CopyToReg &&
794 if (F->getOpcode() == ISD::CopyFromReg) {
797 } else if (F->getOpcode() == ISD::CopyToReg) {
[all...] |
| LegalizeTypes.cpp | [all...] |
| ScheduleDAGSDNodes.h | 68 if (Node->getOpcode() == ISD::EntryToken ||
|
| ScheduleDAGSDNodes.cpp | 114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
389 if (NI->getOpcode() == ISD::TokenFactor)
411 if (SUNode->getOpcode() != ISD::CopyToReg)
485 if(isChain && OpN->getOpcode() == ISD::TokenFactor)
532 if (Node->getOpcode() == ISD::CopyFromReg)
591 if (N && N->getOpcode() == ISD::TokenFactor) {
633 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
[all...] |
| ScheduleDAGRRList.cpp | 288 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) {
416 if (N->getOpcode() == ISD::TokenFactor) {
442 if (N->getOpcode() == ISD::EntryToken)
463 if (N->getOpcode() == ISD::TokenFactor) {
502 if (N->getOpcode() == ISD::EntryToken)
676 case ISD::MERGE_VALUES:
677 case ISD::TokenFactor:
678 case ISD::LIFETIME_START:
679 case ISD::LIFETIME_END:
680 case ISD::CopyToReg
[all...] |
| LegalizeTypes.h | 78 return N->getOpcode() == ISD::TargetConstant;
200 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
287 void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
361 ISD::CondCode &CCCode, DebugLoc dl);
487 ISD::CondCode &CCCode, DebugLoc dl);
660 LoadSDNode *LD, ISD::LoadExtType ExtType);
[all...] |
| ScheduleDAGFast.cpp | 485 if (Node->getOpcode() == ISD::INLINEASM) {
666 (N->getOpcode() == ISD::EntryToken || isPassiveNode(N)))
739 (N->getOpcode() != ISD::EntryToken && !isPassiveNode(N)))
|
| FunctionLoweringInfo.cpp | 68 SmallVector<ISD::OutputArg, 4> Outs;
|
| /external/llvm/include/llvm/Target/ |
| TargetCallingConv.h | 23 namespace ISD {
|
| /external/llvm/lib/MC/ |
| MCELFStreamer.cpp | 136 IndirectSymbolData ISD;
137 ISD.Symbol = Symbol;
138 ISD.SectionData = getCurrentSectionData();
139 getAssembler().getIndirectSymbols().push_back(ISD);
|
| MCMachOStreamer.cpp | 227 IndirectSymbolData ISD;
228 ISD.Symbol = Symbol;
229 ISD.SectionData = getCurrentSectionData();
230 getAssembler().getIndirectSymbols().push_back(ISD);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 102 case ISD::LOAD:
105 case ISD::STORE:
202 // Sign : ISD::SEXTLOAD
203 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
205 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
209 if ((LD->getExtensionType() == ISD::SEXTLOAD))
367 // Sign : ISD::SEXTLOA
[all...] |
| /external/clang/test/CXX/temp/temp.spec/temp.expl.spec/ |
| examples.cpp | 231 namespace ISD {
233 template class BasicStringPiece<int>; // expected-error {{explicit instantiation of undefined template 'spec_vs_expl_inst::ISD::BasicStringPiece<int>'}}
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 19 /// ISD namespace - This namespace contains an enum which represents all of the
22 namespace ISD {
25 /// ISD::NodeType enum - This enum defines the target-independent operators
444 /// 5) ISD::CvtCode indicating the type of conversion to do
716 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 209 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | [all...] |
