| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.cpp | 45 MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
46 : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {}
|
| MBlazeInstrInfo.cpp | 288 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
291 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 107 const TargetInstrInfo *TII = TM.getInstrInfo();
111 TII->get(TargetOpcode::BUNDLE));
|
| MachineTraceMetrics.cpp | 39 : MachineFunctionPass(ID), MF(0), TII(0), TRI(0), MRI(0), Loops(0) {
52 TII = MF->getTarget().getInstrInfo();
58 SchedModel.init(*ST.getSchedModel(), &ST, TII);
775 const TargetInstrInfo *TII,
834 const TargetInstrInfo *TII) {
[all...] |
| RegAllocFast.cpp | 59 const TargetInstrInfo *TII;
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
314 TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) {
629 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
867 TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
[all...] |
| AggressiveAntiDepBreaker.cpp | 121 TII(MF.getTarget().getInstrInfo()),
368 TII->isPredicated(MI)) {
387 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
435 TII->isPredicated(MI);
461 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
[all...] |
| MachineScheduler.cpp | 203 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
249 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
259 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
765 const TargetInstrInfo *TII;
768 LoadClusterMutation(const TargetInstrInfo *tii,
770 : TII(tii), TRI(tri) {}
793 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
808 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
871 const TargetInstrInfo *TII;
[all...] |
| MachineVerifier.cpp | 67 const TargetInstrInfo *TII;
287 TII = TM->getInstrInfo();
543 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
567 !TII->isPredicated(getBundleStart(&MBB->back()))) {
706 if (MI->isTerminator() && !TII->isPredicated(MI)) {
797 if (!TII->verifyInstruction(MI, ErrorInfo))
890 TII->getRegClass(MCID, MONum, TRI, *MF)) {
[all...] |
| RegisterCoalescer.cpp | 83 const TargetInstrInfo* TII;
605 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
645 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
753 if (!TII->isTriviallyReMaterializable(DefMI, AA))
756 if (!DefMI->isSafeToMove(TII, AA, SawStore))
769 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
780 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
[all...] |
| StrongPHIElimination.cpp | 145 const TargetInstrInfo *TII;
235 TII = MF.getTarget().getInstrInfo();
698 TII->get(TargetOpcode::COPY),
767 TII->get(TargetOpcode::COPY),
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| MachineInstr.cpp | [all...] |
| ScheduleDAG.cpp | 38 TII(TM.getInstrInfo()),
59 return &TII->get(Node->getMachineOpcode());
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 307 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
308 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 238 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
434 const TargetInstrInfo *TII) {
435 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
513 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
574 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
|
| FunctionLoweringInfo.cpp | 174 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
176 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 306 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
350 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
357 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
360 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
368 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
369 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
390 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
443 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
447 BuildMI(BB, dl, TII->get(CmpOp))
450 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc)
[all...] |
| AArch64ISelDAGToDAG.cpp | 36 const AArch64InstrInfo *TII;
46 TII(static_cast<const AArch64InstrInfo*>(TM.getInstrInfo())),
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 32 TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
227 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WQM_B64), AMDGPU::EXEC)
462 if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
502 const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
554 const MCInstrDesc *Desc = &TII->get(Opcode);
561 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| PPCISelDAGToDAG.cpp | 227 const TargetInstrInfo &TII = *TM.getInstrInfo();
235 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
236 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
238 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
252 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
263 const TargetInstrInfo &TII = *TM.getInstrInfo();
271 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
272 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
275 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
276 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| FastISel.h | 58 const TargetInstrInfo &TII;
|
| LiveIntervalAnalysis.h | 54 const TargetInstrInfo* TII;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 53 const HexagonInstrInfo *TII;
61 TII(static_cast<const HexagonInstrInfo*>(TM.getInstrInfo())) {
398 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
462 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
539 if (TII->isValidAutoIncImm(LoadedVT, Val))
544 if (TII->isValidAutoIncImm(LoadedVT, Val))
549 if (TII->isValidAutoIncImm(LoadedVT, Val))
554 if (TII->isValidAutoIncImm(LoadedVT, Val))
571 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
646 if (TII->isValidAutoIncImm(StoredVT, Val))
[all...] |
