| /external/llvm/lib/Target/MBlaze/InstPrinter/ |
| MBlazeInstPrinter.cpp | 37 const MCOperand &Op = MI->getOperand(OpNo);
50 const MCOperand &MO = MI->getOperand(OpNo);
59 const MCOperand &MO = MI->getOperand(OpNo);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeDelaySlotFiller.cpp | 70 MachineOperand &mop = candidate->getOperand(op);
134 bool aop_is_reg = a->getOperand(aop).isReg();
137 bool aop_is_def = a->getOperand(aop).isDef();
138 unsigned aop_reg = a->getOperand(aop).getReg();
142 bool mop_is_reg = m->getOperand(mop).isReg();
145 bool mop_is_def = m->getOperand(mop).isDef();
146 unsigned mop_reg = m->getOperand(mop).getReg();
162 if (a->getOperand(aop).isReg()) {
163 unsigned aop_reg = a->getOperand(aop).getReg();
166 if (b->getOperand(bop).isReg() && !b->getOperand(bop).isImplicit())
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCodeEmitter.cpp | 123 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
141 const MachineOperand &MO = MI.getOperand(OpNo);
183 const MachineOperand &MO = MI.getOperand(OpNo);
192 const MachineOperand &MO = MI.getOperand(OpNo);
199 const MachineOperand &MO = MI.getOperand(OpNo);
208 const MachineOperand &MO = MI.getOperand(OpNo);
219 assert(MI.getOperand(OpNo+1).isReg());
220 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
222 const MachineOperand &MO = MI.getOperand(OpNo);
235 assert(MI.getOperand(OpNo+1).isReg())
[all...] |
| PPCCTRLoops.cpp | 284 unsigned DefReg = MPhi->getOperand(0).getReg();
287 MachineBasicBlock *MBB = MPhi->getOperand(i+1).getMBB();
290 MachineInstr *DI = MRI->getVRegDef(MPhi->getOperand(i).getReg());
326 unsigned PredReg = LastI->getOperand(1).getReg();
329 unsigned PredCond = LastI->getOperand(0).getImm();
346 if (!L->contains(IV_Inst->getOperand(2).getMBB())) {
347 InitialValue = &IV_Inst->getOperand(1);
348 IV_Opnd = &IV_Inst->getOperand(3);
350 InitialValue = &IV_Inst->getOperand(3);
351 IV_Opnd = &IV_Inst->getOperand(1)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 231 unsigned Reg = MI->getOperand(OpNo).getReg();
233 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
239 if (!MI->getOperand(OpNo+i).isReg()) continue;
241 unsigned Reg = MI->getOperand(OpNo+i).getReg();
245 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
257 OutMI.addOperand(OutMI.getOperand(0));
258 OutMI.addOperand(OutMI.getOperand(0));
265 assert(Inst.getOperand(0).isReg() &&
266 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 310 isInt32Immediate(N->getOperand(1).getNode(), Imm);
356 SDValue N0 = N->getOperand(0);
357 SDValue N1 = N->getOperand(1);
384 SDValue Srl = N1.getOperand(0);
406 Srl.getOperand(0),
487 BaseReg = N.getOperand(0);
489 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
511 BaseReg = N.getOperand(0);
513 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
516 ShReg = N.getOperand(1)
[all...] |
| MLxExpansionPass.cpp | 89 unsigned Reg = MI->getOperand(1).getReg();
99 Reg = DefMI->getOperand(1).getReg();
105 Reg = DefMI->getOperand(2).getReg();
117 unsigned Reg = MI->getOperand(0).getReg();
128 Reg = UseMI->getOperand(0).getReg();
143 unsigned Reg = MI->getOperand(1).getReg();
156 if (DefMI->getOperand(i + 1).getMBB() == MBB) {
157 unsigned SrcReg = DefMI->getOperand(i).getReg();
165 Reg = DefMI->getOperand(1).getReg();
171 Reg = DefMI->getOperand(2).getReg()
[all...] |
| Thumb2SizeReduction.cpp | 241 const MachineOperand &MO = Def->getOperand(i);
251 const MachineOperand &MO = Use->getOperand(i);
314 const MachineOperand &MO = MI->getOperand(i);
357 if (MI->getOperand(1).getReg() == ARM::SP) {
391 unsigned BaseReg = MI->getOperand(0).getReg();
399 if (MI->getOperand(i).getReg() == BaseReg) {
413 unsigned BaseReg = MI->getOperand(1).getReg();
427 unsigned BaseReg = MI->getOperand(1).getReg();
447 OffsetReg = MI->getOperand(2).getReg();
448 OffsetKill = MI->getOperand(2).isKill()
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 110 return BitConvertToInteger(N->getOperand(0));
124 BitConvertToInteger(N->getOperand(0)),
125 BitConvertToInteger(N->getOperand(1)));
135 SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
138 NewOp, N->getOperand(1));
149 SDValue Op = GetSoftenedFloat(N->getOperand(0));
155 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
156 GetSoftenedFloat(N->getOperand(1)) };
168 SDValue Op = GetSoftenedFloat(N->getOperand(0));
179 SDValue LHS = GetSoftenedFloat(N->getOperand(0))
[all...] |
| LegalizeIntegerTypes.cpp | 155 SDValue Op = SExtPromotedInteger(N->getOperand(0));
157 Op.getValueType(), Op, N->getOperand(1));
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
164 Op.getValueType(), Op, N->getOperand(1));
181 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
207 SDValue InOp = N->getOperand(0);
238 GetSplitVector(N->getOperand(0), Lo, Hi);
264 SDValue Op = GetPromotedInteger(N->getOperand(0))
[all...] |
| TargetLowering.cpp | 273 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
283 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
330 Op.getNode()->getOperand(0)),
332 Op.getNode()->getOperand(1)));
396 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
399 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
402 return TLO.CombineTo(Op, Op.getOperand(0));
409 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
413 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
421 return TLO.CombineTo(Op, Op.getOperand(0))
[all...] |
| LegalizeVectorTypes.cpp | 129 SDValue LHS = GetScalarizedVector(N->getOperand(0));
130 SDValue RHS = GetScalarizedVector(N->getOperand(1));
136 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
137 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
138 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
152 NewVT, N->getOperand(0));
157 SDValue InOp = N->getOperand(0);
167 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
171 N->getOperand(3),
172 N->getOperand(4)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 114 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
123 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
127 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
129 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
130 Op.getOperand(2));
132 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
133 Op.getOperand(2));
135 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
136 Op.getOperand(2));
138 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1)
[all...] |
| SILowerControlFlow.cpp | 179 unsigned Reg = MI.getOperand(0).getReg();
180 unsigned Vcc = MI.getOperand(1).getReg();
189 Skip(MI, MI.getOperand(2));
197 unsigned Dst = MI.getOperand(0).getReg();
198 unsigned Src = MI.getOperand(1).getReg();
207 Skip(MI, MI.getOperand(2));
216 unsigned Dst = MI.getOperand(0).getReg();
217 unsigned Src = MI.getOperand(1).getReg();
230 unsigned Dst = MI.getOperand(0).getReg();
231 unsigned Vcc = MI.getOperand(1).getReg()
[all...] |
| AMDILPeepholeOptimizer.cpp | 243 Constant *CV = dyn_cast<Constant>(CI->getOperand(0));
323 StringRef calleeName = CI->getOperand(CI->getNumOperands()-1)->getName();
334 Constant *CV = dyn_cast<Constant>(CI->getOperand(0));
346 ConstantInt *CV = dyn_cast<ConstantInt>(CI->getOperand(0));
360 Function *F = dyn_cast<Function>(CI->getOperand(CI->getNumOperands()-1));
399 shift = dyn_cast<Constant>(base->getOperand(1));
401 mask = dyn_cast<Constant>(base->getOperand(1));
410 src = dyn_cast<Instruction>(base->getOperand(0));
424 shift = dyn_cast<Constant>(src->getOperand(1));
425 src = dyn_cast<Instruction>(src->getOperand(0))
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 109 if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
110 FrameReg = MI.getOperand(OpNo+2).getReg();
127 Offset += MI.getOperand(OpNo + 1).getImm();
141 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
142 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCompares.cpp | 219 !isa<ConstantInt>(GEP->getOperand(1)) ||
220 !cast<ConstantInt>(GEP->getOperand(1))->isZero() ||
221 isa<Constant>(GEP->getOperand(2)))
231 ConstantInt *Idx = dyn_cast<ConstantInt>(GEP->getOperand(i));
279 Constant *CompareRHS = cast<Constant>(ICI.getOperand(1));
366 Value *Idx = GEP->getOperand(2);
488 if (ConstantInt *CI = dyn_cast<ConstantInt>(GEP->getOperand(i))) {
509 Value *VariableIdx = GEP->getOperand(i);
516 ConstantInt *CI = dyn_cast<ConstantInt>(GEP->getOperand(i));
585 RHS = BCI->getOperand(0)
[all...] |
| InstCombineMulDivRem.cpp | 48 if (I->isLogicalShift() && isKnownToBeAPowerOfTwo(I->getOperand(0))) {
51 if (Value *V2 = simplifyValueKnownNonZero(I->getOperand(0), IC)) {
100 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
116 if (Constant *ShOp = dyn_cast<Constant>(SI->getOperand(1)))
117 return BinaryOperator::CreateMul(SI->getOperand(0),
191 (BO->getOperand(1) == Op1C || BO->getOperand(1) == Neg) &&
194 Value *Op0BO = BO->getOperand(0), *Op1BO = BO->getOperand(1)
[all...] |
| InstCombineAndOrXor.cpp | 135 Value *X = Op->getOperand(0);
259 Value *ShVal = Op->getOperand(0);
349 !isa<ConstantInt>(LHSI->getOperand(1))) return 0;
351 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1));
386 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold");
387 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold");
502 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
504 X = I->getOperand(0);
514 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
516 X = I->getOperand(0)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 77 const MachineOperand &MO = MI->getOperand(OpNo);
145 if (!MI->getOperand(OpNo).isReg() ||
147 !MI->getOperand(OpNo+1).isReg())
154 if (MI->getOperand(OpNo).isImm())
171 const MachineOperand &Base = MI->getOperand(OpNo);
172 const MachineOperand &Offset = MI->getOperand(OpNo+1);
255 const MachineOperand &MO1 = MI->getOperand(OpNo);
256 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
266 const MachineOperand &MO = MI->getOperand(OpNo);
279 const MachineOperand &MO = MI->getOperand(OpNo)
[all...] |
| /external/llvm/lib/Analysis/ |
| Loads.cpp | 114 if (AreEquivalentAddressValues(LI->getOperand(0), V)) return true;
116 if (AreEquivalentAddressValues(SI->getOperand(1), V)) return true;
171 if (AreEquivalentAddressValues(LI->getOperand(0), Ptr)) {
180 if (AreEquivalentAddressValues(SI->getOperand(1), Ptr)) {
182 return SI->getOperand(0);
189 (isa<AllocaInst>(SI->getOperand(1)) ||
190 isa<GlobalVariable>(SI->getOperand(1))))
|
| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 28 const MCOperand &Op = MI->getOperand(OpNo);
49 unsigned Imm = MI->getOperand(OpNum).getImm();
71 const MCOperand &Op = MI->getOperand(OpNo);
95 L.i = MI->getOperand(OpNo).getImm();
111 switch (MI->getOperand(OpNo).getImm()) {
142 const MCOperand &Op = MI->getOperand(OpNo);
151 int sel = MI->getOperand(OpNo).getImm();
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 171 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
236 return MI.getOperand(Op).getReg() == ARM::CPSR;
242 unsigned SoImm = MI.getOperand(Op).getImm();
258 unsigned SoImm = MI.getOperand(Op).getImm();
283 return 64 - MI.getOperand(Op).getImm();
436 const MCOperand &MO = MI.getOperand(OpIdx);
437 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
465 const MCOperand &MO = MI.getOperand(OpIdx);
501 const MCOperand MO = MI.getOperand(OpIdx);
513 const MCOperand MO = MI.getOperand(OpIdx)
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 70 unsigned SrcReg = MI.getOperand(OpNum).getReg();
71 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
167 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
168 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
182 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
183 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
197 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
198 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
303 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
304 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg)
[all...] |
| /external/llvm/unittests/Analysis/ |
| ScalarEvolutionTest.cpp | 68 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(),
70 EXPECT_EQ(cast<SCEVConstant>(M1->getOperand(0))->getValue()->getZExtValue(),
72 EXPECT_EQ(cast<SCEVConstant>(M2->getOperand(0))->getValue()->getZExtValue(),
76 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
77 EXPECT_EQ(cast<SCEVUnknown>(M1->getOperand(1))->getValue(), V1);
78 EXPECT_EQ(cast<SCEVUnknown>(M2->getOperand(1))->getValue(), V2);
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
86 EXPECT_EQ(cast<SCEVUnknown>(M1->getOperand(1))->getValue(), V0);
87 EXPECT_EQ(cast<SCEVUnknown>(M2->getOperand(1))->getValue(), V0);
148 EXPECT_EQ(Product->getOperand(0), SE.getAddExpr(Sum))
[all...] |
