| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrFormats.td | 55 string asmstr> : Instruction {
71 let AsmString = asmstr;
78 dag outs, dag ins, string asmstr, list<dag> pattern>
79 : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> {
93 dag outs, dag ins, string asmstr, list<dag> pattern>
94 : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>;
97 dag outs, dag ins, string asmstr, list<dag> pattern>
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
101 dag outs, dag ins, string asmstr, list<dag> pattern>
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrFormats.td | 14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
24 let AsmString = asmstr;
57 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
69 let AsmString = asmstr;
86 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
88 : I<opcode, OOL, IOL, asmstr, itin> {
98 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
99 : I<opcode, OOL, IOL, asmstr, BrB> {
116 string asmstr>
117 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrFormats.td | 13 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
20 let AsmString = asmstr;
27 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : InstXCore<0, outs, ins, asmstr, pattern> {
36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 : InstXCore<2, outs, ins, asmstr, pattern> {
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 : InstXCore<4, outs, ins, asmstr, pattern>
[all...] |
| /external/llvm/test/TableGen/ |
| Slice.td | 14 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
19 string AssemblyString = asmstr;
64 multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
66 !strconcat(asmstr, "\t$dst, $src"),
69 !strconcat(asmstr, "\t$dst, $src"),
73 multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
75 !strconcat(asmstr, "\t$dst, $src"),
78 !strconcat(asmstr, "\t$dst, $src"),
82 multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> :
83 scalar<opcode, asmstr, patterns>
[all...] |
| cast.td | 15 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
20 string AssemblyString = asmstr;
66 multiclass arith<bits<8> opcode, string asmstr, string Intr> {
68 !strconcat(asmstr, "\t$dst, $src1, $src2"),
72 !strconcat(asmstr, "\t$dst, $src1, $src2"),
78 class IntInst<bits<8> opcode, string asmstr, Intrinsic Intr> :
80 !strconcat(asmstr, "\t$dst, $src1, $src2"),
84 multiclass arith_int<bits<8> opcode, string asmstr, string Intr> {
85 def PS_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_ps"))>;
87 def PD_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_pd"))>
[all...] |
| TargetInstrSpec.td | 16 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
21 string AssemblyString = asmstr;
79 multiclass arith<bits<8> opcode, string asmstr, string intr, list<dag> patterns> {
81 !strconcat(asmstr, "\t$dst, $src1, $src2"),
88 !strconcat(asmstr, "\t$dst, $src1, $src2"),
|
| MultiPat.td | 24 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
29 string AssemblyString = asmstr;
91 class Base<bits<8> opcode, dag opnds, dag iopnds, string asmstr, Intrinsic intr,
93 : Inst<opcode, opnds, iopnds, asmstr,
105 multiclass arith<bits<8> opcode, string asmstr, string intr, list<list<dag>> patterns> {
107 !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast<Intrinsic>(!subst("SUFFIX", "_ps", intr)), patterns>;
110 !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast<Intrinsic>(!subst("SUFFIX", "_pd", intr)), patterns>;
|
| TargetInstrInfo.td | 60 class Inst<dag opnds, string asmstr, bits<8> opcode,
63 string AssemblyString = asmstr;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrFormats.td | 84 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
91 let AsmString = asmstr;
178 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
180 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD>;
183 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
185 : LDInst<outs, ins, asmstr, pattern, cstr>;
187 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
189 : LDInst<outs, ins, asmstr, pattern, cstr>;
193 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
195 : LDInst<outs, ins, asmstr, pattern, cstr>
[all...] |
| HexagonInstrFormatsV4.td | 31 class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
33 : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV>;
35 class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
37 : NVInst<outs, ins, asmstr, pattern, cstr>;
40 class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
42 : NVInst<outs, ins, asmstr, pattern, cstr>;
46 class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
48 : NVInst<outs, ins, asmstr, pattern, cstr>;
51 class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
53 : NVInst<outs, ins, asmstr, pattern, cstr>
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrFormats.td | 10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
20 let AsmString = asmstr;
29 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
30 : InstSP<outs, ins, asmstr, pattern> {
40 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
41 : F2<outs, ins, asmstr, pattern> {
49 class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr,
50 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
65 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
66 : InstSP<outs, ins, asmstr, pattern>
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrFormats.td | 20 class A64Inst<dag outs, dag ins, string asmstr, list<dag> patterns,
40 let AsmString = asmstr;
71 class A64InstRd<dag outs, dag ins, string asmstr,
73 : A64Inst<outs, ins, asmstr, patterns, itin> {
79 class A64InstRt<dag outs, dag ins, string asmstr,
81 : A64Inst<outs, ins, asmstr, patterns, itin> {
88 class A64InstRdn<dag outs, dag ins, string asmstr,
90 : A64InstRd<outs, ins, asmstr, patterns, itin> {
97 class A64InstRtn<dag outs, dag ins, string asmstr,
99 : A64InstRt<outs, ins, asmstr, patterns, itin>
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.td | 39 class FI816_ins_base<bits<3> _func, string asmstr,
41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
45 class FI816_SP_ins<bits<3> _func, string asmstr,
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
54 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
57 !strconcat(asmstr, asmstr2), [], itin>;
59 class FRI16_ins<bits<5> op, string asmstr,
61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
63 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
66 !strconcat(asmstr, asmstr2), [], itin>
[all...] |
| Mips16InstrFormats.td | 36 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
45 let AsmString = asmstr;
55 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
57 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
72 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
74 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
82 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
84 MipsInst16_32<outs, ins, asmstr, pattern, itin>
92 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
93 MipsInst16<outs, ins, asmstr, pattern, IIPseudo>
[all...] |
| MipsInstrFormats.td | 40 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
58 let AsmString = asmstr;
76 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
78 MipsInst<outs, ins, asmstr, pattern, itin, f> {
100 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
101 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
109 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
111 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
133 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
134 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrFormats.td | 54 class MBlazeInst<bits<6> op, Format form, dag outs, dag ins, string asmstr,
73 let AsmString = asmstr;
84 class MBlazePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
85 MBlazeInst<0x0, FPseudo, outs, ins, asmstr, pattern, IIC_Pseudo>;
91 class TA<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
93 MBlazeInst<op,FRRR,outs, ins, asmstr, pattern, itin>
109 class TB<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
111 MBlazeInst<op, FRRI, outs, ins, asmstr, pattern, itin>
127 class TAR<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
129 TA<op, flags, outs, ins, asmstr, pattern, itin
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterInlineAsm.cpp | 140 static void EmitMSInlineAsmStr(const char *AsmStr, const MachineInstr *MI,
147 const char *LastEmitted = AsmStr; // One past the last character emitted.
187 Twine(AsmStr) + "'");
192 Twine(AsmStr) + "'");
228 Msg << "invalid operand in inline asm: '" << AsmStr << "'";
238 static void EmitGCCInlineAsmStr(const char *AsmStr, const MachineInstr *MI,
243 const char *LastEmitted = AsmStr; // One past the last character emitted.
281 Twine(AsmStr) + "'");
316 " string: '" + Twine(AsmStr) + "'");
331 Twine(AsmStr) + "'")
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXVector.td | 18 class NVPTXVecInst<dag outs, dag ins, string asmstr, list<dag> pattern,
20 : NVPTXInst<outs, ins, asmstr, pattern> {
241 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
244 asmstr.s,
248 class VecShiftOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass1,
251 asmstr.s,
255 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
258 asmstr.s,
261 multiclass IntBinVOp<string asmstr, SDNode OpNode,
264 def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs
[all...] |
| NVPTXInstrFormats.td | 23 class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
30 let AsmString = asmstr;
|
| /external/llvm/docs/ |
| TableGenFundamentals.rst | 558 class inst<int opc, string asmstr, dag operandlist>;
560 multiclass ri_inst<int opc, string asmstr> {
561 def _rr : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
563 def _ri : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
584 class inst<int opc, string asmstr, dag operandlist>;
586 class rrinst<int opc, string asmstr>
587 : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
590 class riinst<int opc, string asmstr>
591 : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
|
| /prebuilts/ndk/4/platforms/android-3/arch-arm/usr/include/machine/ |
| asm.h | 92 #define ASMSTR .asciz
|
| /prebuilts/ndk/4/platforms/android-4/arch-arm/usr/include/machine/ |
| asm.h | 92 #define ASMSTR .asciz
|
| /prebuilts/ndk/4/platforms/android-5/arch-arm/usr/include/machine/ |
| asm.h | 92 #define ASMSTR .asciz
|
| /prebuilts/ndk/4/platforms/android-5/arch-x86/usr/include/machine/ |
| asm.h | 119 #define ASMSTR .asciz
|
| /prebuilts/ndk/4/platforms/android-8/arch-arm/usr/include/machine/ |
| asm.h | 92 #define ASMSTR .asciz
|
