| /external/clang/test/SemaTemplate/ |
| instantiate-subscript.cpp | 4 struct Sub0 {
24 template struct Subscript0<Sub0, int, int&>;
26 template struct Subscript0<Sub1, Sub0, long&>; // expected-note{{instantiation}}
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstructions.td | 200 (vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1))),
202 (vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1)
210 (vecType (IMPLICIT_DEF)), elemClass:$x, sub0), elemClass:$y, sub1),
216 (vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
222 (vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1),
230 (vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
242 (vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1)
[all...] |
| SIRegisterInfo.td | 46 def SGPR_64 : RegisterTuples<[sub0, sub1],
51 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
58 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
69 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
93 def VGPR_64 : RegisterTuples<[sub0, sub1],
98 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
105 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
116 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
|
| SIInstrInfo.cpp | 46 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
53 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
58 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
62 AMDGPU::sub0, AMDGPU::sub1, 0
|
| R600RegisterInfo.td | 22 let SubRegIndices = [sub0, sub1, sub2, sub3];
129 [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
|
| AMDGPURegisterInfo.cpp | 54 case 0: return AMDGPU::sub0;
|
| R600RegisterInfo.cpp | 93 case 0: return AMDGPU::sub0;
|
| SIInstructions.td | [all...] |
| SILowerControlFlow.cpp | 383 .addReg(TRI->getSubReg(Vec, AMDGPU::sub0) + Off)
401 .addReg(TRI->getSubReg(Dst, AMDGPU::sub0) + Off, RegState::Define)
|
| R600MachineScheduler.cpp | 216 case AMDGPU::sub0:
|
| R600Instructions.td | 595 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
601 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
[all...] |
| AMDILISelDAGToDAG.cpp | 176 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
|
| SIISelLowering.cpp | 167 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
|
| /external/icu4c/common/ |
| locdispnames.cpp | 470 static const UChar sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 } ; /* {0} */ local
530 UChar *p0=u_strstr(pattern, sub0);
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
