1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This file was originally auto-generated from a GPU register header file and 10 // all the instruction definitions were originally commented out. Instructions 11 // that are not yet supported remain commented out. 12 //===----------------------------------------------------------------------===// 13 14 class InterpSlots { 15 int P0 = 2; 16 int P10 = 0; 17 int P20 = 1; 18 } 19 def INTERP : InterpSlots; 20 21 def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23 } 24 25 def isSI : Predicate<"Subtarget.device()" 26 "->getGeneration() == AMDGPUDeviceInfo::HD7XXX">; 27 28 let Predicates = [isSI] in { 29 30 let neverHasSideEffects = 1 in { 31 32 let isMoveImm = 1 in { 33 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 34 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 35 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 36 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 37 } // End isMoveImm = 1 38 39 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 40 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 41 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 42 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 43 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 44 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 45 } // End neverHasSideEffects = 1 46 47 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 48 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 49 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 50 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 51 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 52 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 53 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 54 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 55 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 56 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 57 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 58 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 59 //def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 60 //def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 61 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 62 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 63 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 64 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 65 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 66 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 67 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 68 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 69 70 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 71 72 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 73 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 74 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 75 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 76 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 77 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 78 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 79 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 80 81 } // End hasSideEffects = 1 82 83 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 84 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 85 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 86 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 87 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 88 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 89 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 90 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 91 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 92 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 93 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 94 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 95 96 /* 97 This instruction is disabled for now until we can figure out how to teach 98 the instruction selector to correctly use the S_CMP* vs V_CMP* 99 instructions. 100 101 When this instruction is enabled the code generator sometimes produces this 102 invalid sequence: 103 104 SCC = S_CMPK_EQ_I32 SGPR0, imm 105 VCC = COPY SCC 106 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 107 108 def S_CMPK_EQ_I32 : SOPK < 109 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 110 "S_CMPK_EQ_I32", 111 [(set SCCReg:$dst, (setcc SReg_32:$src0, imm:$src1, SETEQ))] 112 >; 113 */ 114 115 let isCompare = 1 in { 116 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 117 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 118 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 119 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 120 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 121 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 122 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 123 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 124 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 125 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 126 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 127 } // End isCompare = 1 128 129 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 130 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 131 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 132 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 133 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 134 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 135 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 136 //def EXP : EXP_ <0x00000000, "EXP", []>; 137 138 let isCompare = 1 in { 139 140 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 141 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_LT>; 142 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_EQ>; 143 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_LE>; 144 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_GT>; 145 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", f32, COND_NE>; 146 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_GE>; 147 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32">; 148 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32">; 149 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 150 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 151 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 152 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 153 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_NE>; 154 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 155 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 156 157 let hasSideEffects = 1, Defs = [EXEC] in { 158 159 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 160 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 161 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 162 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 163 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 164 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 165 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 166 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 167 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 168 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 169 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 170 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 171 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 172 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 173 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 174 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 175 176 } // End hasSideEffects = 1, Defs = [EXEC] 177 178 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 179 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64">; 180 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64">; 181 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64">; 182 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64">; 183 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 184 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64">; 185 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64">; 186 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64">; 187 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 188 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 189 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 190 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 191 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64">; 192 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 193 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 194 195 let hasSideEffects = 1, Defs = [EXEC] in { 196 197 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 198 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 199 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 200 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 201 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 202 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 203 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 204 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 205 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 206 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 207 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 208 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 209 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 210 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 211 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 212 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 213 214 } // End hasSideEffects = 1, Defs = [EXEC] 215 216 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 217 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 218 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 219 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 220 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 221 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 222 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 223 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 224 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 225 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 226 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 227 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 228 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 229 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 230 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 231 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 232 233 let hasSideEffects = 1, Defs = [EXEC] in { 234 235 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 236 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 237 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 238 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 239 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 240 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 241 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 242 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 243 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 244 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 245 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 246 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 247 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 248 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 249 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 250 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 251 252 } // End hasSideEffects = 1, Defs = [EXEC] 253 254 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 255 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 256 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 257 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 258 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 259 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 260 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 261 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 262 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 263 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 264 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 265 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 266 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 267 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 268 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 269 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 270 271 let hasSideEffects = 1, Defs = [EXEC] in { 272 273 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 274 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 275 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 276 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 277 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 278 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 279 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 280 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 281 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 282 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 283 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 284 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 285 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 286 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 287 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 288 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 289 290 } // End hasSideEffects = 1, Defs = [EXEC] 291 292 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 293 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_LT>; 294 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 295 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_LE>; 296 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_GT>; 297 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 298 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_GE>; 299 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 300 301 let hasSideEffects = 1, Defs = [EXEC] in { 302 303 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 304 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 305 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 306 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 307 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 308 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 309 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 310 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 311 312 } // End hasSideEffects = 1, Defs = [EXEC] 313 314 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 315 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64">; 316 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64">; 317 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64">; 318 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64">; 319 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64">; 320 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64">; 321 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 322 323 let hasSideEffects = 1, Defs = [EXEC] in { 324 325 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 326 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 327 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 328 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 329 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 330 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 331 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 332 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 333 334 } // End hasSideEffects = 1, Defs = [EXEC] 335 336 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 337 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32">; 338 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32">; 339 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32">; 340 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32">; 341 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32">; 342 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32">; 343 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 344 345 let hasSideEffects = 1, Defs = [EXEC] in { 346 347 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 348 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 349 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 350 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 351 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 352 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 353 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 354 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 355 356 } // End hasSideEffects = 1, Defs = [EXEC] 357 358 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 359 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64">; 360 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64">; 361 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64">; 362 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64">; 363 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64">; 364 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64">; 365 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 366 367 let hasSideEffects = 1, Defs = [EXEC] in { 368 369 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 370 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 371 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 372 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 373 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 374 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 375 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 376 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 377 378 } // End hasSideEffects = 1, Defs = [EXEC] 379 380 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 381 382 let hasSideEffects = 1, Defs = [EXEC] in { 383 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 384 } // End hasSideEffects = 1, Defs = [EXEC] 385 386 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 387 388 let hasSideEffects = 1, Defs = [EXEC] in { 389 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 390 } // End hasSideEffects = 1, Defs = [EXEC] 391 392 } // End isCompare = 1 393 394 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 395 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 396 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 397 def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 398 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 399 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 400 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 401 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 402 //def BUFFER_LOAD_UBYTE : MUBUF_ <0x00000008, "BUFFER_LOAD_UBYTE", []>; 403 //def BUFFER_LOAD_SBYTE : MUBUF_ <0x00000009, "BUFFER_LOAD_SBYTE", []>; 404 //def BUFFER_LOAD_USHORT : MUBUF_ <0x0000000a, "BUFFER_LOAD_USHORT", []>; 405 //def BUFFER_LOAD_SSHORT : MUBUF_ <0x0000000b, "BUFFER_LOAD_SSHORT", []>; 406 def BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 407 def BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 408 def BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 409 //def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>; 410 //def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>; 411 //def BUFFER_STORE_DWORD : MUBUF_ <0x0000001c, "BUFFER_STORE_DWORD", []>; 412 //def BUFFER_STORE_DWORDX2 : MUBUF_DWORDX2 <0x0000001d, "BUFFER_STORE_DWORDX2", []>; 413 //def BUFFER_STORE_DWORDX4 : MUBUF_DWORDX4 <0x0000001e, "BUFFER_STORE_DWORDX4", []>; 414 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 415 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 416 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 417 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 418 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 419 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 420 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 421 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 422 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 423 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 424 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 425 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 426 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 427 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 428 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 429 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 430 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 431 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 432 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 433 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 434 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 435 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 436 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 437 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 438 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 439 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 440 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 441 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 442 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 443 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 444 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 445 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 446 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 447 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 448 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 449 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 450 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 451 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 452 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 453 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 454 //def TBUFFER_STORE_FORMAT_X : MTBUF_ <0x00000004, "TBUFFER_STORE_FORMAT_X", []>; 455 //def TBUFFER_STORE_FORMAT_XY : MTBUF_ <0x00000005, "TBUFFER_STORE_FORMAT_XY", []>; 456 //def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>; 457 //def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>; 458 459 let mayLoad = 1 in { 460 461 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SReg_32>; 462 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 463 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 464 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 465 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 466 467 defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 468 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SReg_32 469 >; 470 471 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 472 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 473 >; 474 475 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 476 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 477 >; 478 479 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 480 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 481 >; 482 483 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 484 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 485 >; 486 487 } // mayLoad = 1 488 489 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 490 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 491 //def IMAGE_LOAD : MIMG_NoPattern_ <"IMAGE_LOAD", 0x00000000>; 492 //def IMAGE_LOAD_MIP : MIMG_NoPattern_ <"IMAGE_LOAD_MIP", 0x00000001>; 493 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 494 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 495 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 496 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 497 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 498 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 499 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 500 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 501 //def IMAGE_GET_RESINFO : MIMG_NoPattern_ <"IMAGE_GET_RESINFO", 0x0000000e>; 502 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 503 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 504 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 505 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 506 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 507 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 508 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 509 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 510 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 511 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 512 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 513 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 514 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 515 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 516 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 517 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 518 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 519 def IMAGE_SAMPLE : MIMG_Load_Helper <0x00000020, "IMAGE_SAMPLE">; 520 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 521 def IMAGE_SAMPLE_D : MIMG_Load_Helper <0x00000022, "IMAGE_SAMPLE_D">; 522 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 523 def IMAGE_SAMPLE_L : MIMG_Load_Helper <0x00000024, "IMAGE_SAMPLE_L">; 524 def IMAGE_SAMPLE_B : MIMG_Load_Helper <0x00000025, "IMAGE_SAMPLE_B">; 525 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 526 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 527 def IMAGE_SAMPLE_C : MIMG_Load_Helper <0x00000028, "IMAGE_SAMPLE_C">; 528 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 529 //def IMAGE_SAMPLE_C_D : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D", 0x0000002a>; 530 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 531 def IMAGE_SAMPLE_C_L : MIMG_Load_Helper <0x0000002c, "IMAGE_SAMPLE_C_L">; 532 def IMAGE_SAMPLE_C_B : MIMG_Load_Helper <0x0000002d, "IMAGE_SAMPLE_C_B">; 533 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 534 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 535 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 536 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 537 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 538 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 539 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 540 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 541 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 542 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 543 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 544 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 545 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 546 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 547 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 548 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 549 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 550 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 551 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 552 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 553 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 554 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 555 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 556 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 557 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 558 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 559 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 560 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 561 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 562 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 563 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 564 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 565 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 566 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 567 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 568 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 569 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 570 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 571 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 572 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 573 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 574 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 575 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 576 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 577 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 578 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 579 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 580 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 581 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 582 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 583 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 584 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 585 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 586 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 587 588 589 let neverHasSideEffects = 1, isMoveImm = 1 in { 590 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 591 } // End neverHasSideEffects = 1, isMoveImm = 1 592 593 defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 594 //defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>; 595 //defm V_CVT_F64_I32 : VOP1_64 <0x00000004, "V_CVT_F64_I32", []>; 596 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 597 [(set VReg_32:$dst, (sint_to_fp VSrc_32:$src0))] 598 >; 599 //defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", []>; 600 //defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", []>; 601 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 602 [(set (i32 VReg_32:$dst), (fp_to_sint VSrc_32:$src0))] 603 >; 604 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 605 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 606 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 607 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 608 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 609 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 610 //defm V_CVT_F32_F64 : VOP1_32 <0x0000000f, "V_CVT_F32_F64", []>; 611 //defm V_CVT_F64_F32 : VOP1_64 <0x00000010, "V_CVT_F64_F32", []>; 612 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 613 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 614 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 615 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 616 //defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 617 //defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 618 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 619 [(set VReg_32:$dst, (AMDGPUfract VSrc_32:$src0))] 620 >; 621 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", []>; 622 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 623 [(set VReg_32:$dst, (fceil VSrc_32:$src0))] 624 >; 625 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 626 [(set VReg_32:$dst, (frint VSrc_32:$src0))] 627 >; 628 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 629 [(set VReg_32:$dst, (ffloor VSrc_32:$src0))] 630 >; 631 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 632 [(set VReg_32:$dst, (fexp2 VSrc_32:$src0))] 633 >; 634 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 635 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 636 [(set VReg_32:$dst, (flog2 VSrc_32:$src0))] 637 >; 638 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 639 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 640 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 641 [(set VReg_32:$dst, (fdiv FP_ONE, VSrc_32:$src0))] 642 >; 643 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 644 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 645 defm V_RSQ_LEGACY_F32 : VOP1_32 < 646 0x0000002d, "V_RSQ_LEGACY_F32", 647 [(set VReg_32:$dst, (int_AMDGPU_rsq VSrc_32:$src0))] 648 >; 649 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 650 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", []>; 651 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 652 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 653 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 654 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", []>; 655 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", []>; 656 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 657 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 658 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 659 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 660 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 661 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 662 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 663 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 664 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 665 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 666 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 667 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 668 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 669 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 670 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 671 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 672 673 def V_INTERP_P1_F32 : VINTRP < 674 0x00000000, 675 (outs VReg_32:$dst), 676 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 677 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 678 []> { 679 let DisableEncoding = "$m0"; 680 } 681 682 def V_INTERP_P2_F32 : VINTRP < 683 0x00000001, 684 (outs VReg_32:$dst), 685 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 686 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 687 []> { 688 689 let Constraints = "$src0 = $dst"; 690 let DisableEncoding = "$src0,$m0"; 691 692 } 693 694 def V_INTERP_MOV_F32 : VINTRP < 695 0x00000002, 696 (outs VReg_32:$dst), 697 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 698 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 699 []> { 700 let DisableEncoding = "$m0"; 701 } 702 703 //def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 704 705 let isTerminator = 1 in { 706 707 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 708 [(IL_retflag)]> { 709 let SIMM16 = 0; 710 let isBarrier = 1; 711 let hasCtrlDep = 1; 712 } 713 714 let isBranch = 1 in { 715 def S_BRANCH : SOPP < 716 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 717 [(br bb:$target)]> { 718 let isBarrier = 1; 719 } 720 721 let DisableEncoding = "$scc" in { 722 def S_CBRANCH_SCC0 : SOPP < 723 0x00000004, (ins brtarget:$target, SCCReg:$scc), 724 "S_CBRANCH_SCC0 $target", [] 725 >; 726 def S_CBRANCH_SCC1 : SOPP < 727 0x00000005, (ins brtarget:$target, SCCReg:$scc), 728 "S_CBRANCH_SCC1 $target", 729 [] 730 >; 731 } // End DisableEncoding = "$scc" 732 733 def S_CBRANCH_VCCZ : SOPP < 734 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 735 "S_CBRANCH_VCCZ $target", 736 [] 737 >; 738 def S_CBRANCH_VCCNZ : SOPP < 739 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 740 "S_CBRANCH_VCCNZ $target", 741 [] 742 >; 743 744 let DisableEncoding = "$exec" in { 745 def S_CBRANCH_EXECZ : SOPP < 746 0x00000008, (ins brtarget:$target, EXECReg:$exec), 747 "S_CBRANCH_EXECZ $target", 748 [] 749 >; 750 def S_CBRANCH_EXECNZ : SOPP < 751 0x00000009, (ins brtarget:$target, EXECReg:$exec), 752 "S_CBRANCH_EXECNZ $target", 753 [] 754 >; 755 } // End DisableEncoding = "$exec" 756 757 758 } // End isBranch = 1 759 } // End isTerminator = 1 760 761 //def S_BARRIER : SOPP_ <0x0000000a, "S_BARRIER", []>; 762 let hasSideEffects = 1 in { 763 def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16", 764 [] 765 >; 766 } // End hasSideEffects 767 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 768 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 769 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 770 //def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>; 771 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 772 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 773 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 774 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 775 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 776 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 777 778 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 779 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 780 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 781 [] 782 >{ 783 let DisableEncoding = "$vcc"; 784 } 785 786 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 787 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 788 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 789 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 790 [(set (i32 VReg_32:$dst), (select (i1 SSrc_64:$src2), 791 VSrc_32:$src1, VSrc_32:$src0))] 792 >; 793 794 //f32 pattern for V_CNDMASK_B32_e64 795 def : Pat < 796 (f32 (select (i1 SSrc_64:$src2), VSrc_32:$src1, VSrc_32:$src0)), 797 (V_CNDMASK_B32_e64 VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2) 798 >; 799 800 defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 801 defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 802 803 let isCommutable = 1 in { 804 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 805 [(set VReg_32:$dst, (fadd VSrc_32:$src0, VReg_32:$src1))] 806 >; 807 } // End isCommutable = 1 808 809 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 810 [(set VReg_32:$dst, (fsub VSrc_32:$src0, VReg_32:$src1))] 811 >; 812 813 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", []>; 814 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 815 816 let isCommutable = 1 in { 817 818 defm V_MUL_LEGACY_F32 : VOP2_32 < 819 0x00000007, "V_MUL_LEGACY_F32", 820 [(set VReg_32:$dst, (int_AMDGPU_mul VSrc_32:$src0, VReg_32:$src1))] 821 >; 822 823 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 824 [(set VReg_32:$dst, (fmul VSrc_32:$src0, VReg_32:$src1))] 825 >; 826 827 } // End isCommutable = 1 828 829 //defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", []>; 830 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 831 //defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", []>; 832 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 833 834 let isCommutable = 1 in { 835 836 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 837 [(set VReg_32:$dst, (AMDGPUfmin VSrc_32:$src0, VReg_32:$src1))] 838 >; 839 840 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 841 [(set VReg_32:$dst, (AMDGPUfmax VSrc_32:$src0, VReg_32:$src1))] 842 >; 843 844 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 845 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 846 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", []>; 847 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>; 848 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>; 849 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>; 850 851 } // End isCommutable = 1 852 853 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", []>; 854 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", []>; 855 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", []>; 856 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", []>; 857 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 858 [(set VReg_32:$dst, (shl VSrc_32:$src0, (i32 VReg_32:$src1)))] 859 >; 860 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", []>; 861 862 let isCommutable = 1 in { 863 864 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 865 [(set VReg_32:$dst, (and VSrc_32:$src0, VReg_32:$src1))] 866 >; 867 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 868 [(set VReg_32:$dst, (or VSrc_32:$src0, VReg_32:$src1))] 869 >; 870 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 871 [(set VReg_32:$dst, (xor VSrc_32:$src0, VReg_32:$src1))] 872 >; 873 874 } // End isCommutable = 1 875 876 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 877 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 878 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 879 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 880 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 881 //defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 882 //defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 883 let Defs = [VCC] in { // Carry-out goes to VCC 884 885 let isCommutable = 1 in { 886 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", 887 [(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))] 888 >; 889 } // End isCommutable = 1 890 891 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", 892 [(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))] 893 >; 894 895 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", []>; 896 let Uses = [VCC] in { // Carry-out comes from VCC 897 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>; 898 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>; 899 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", []>; 900 } // End Uses = [VCC] 901 } // End Defs = [VCC] 902 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 903 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 904 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 905 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 906 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 907 [(set VReg_32:$dst, (int_SI_packf16 VSrc_32:$src0, VReg_32:$src1))] 908 >; 909 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 910 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 911 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 912 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 913 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 914 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 915 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 916 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 917 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 918 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 919 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 920 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 921 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 922 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 923 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 924 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 925 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 926 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 927 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 928 929 let neverHasSideEffects = 1 in { 930 931 def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 932 def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 933 //def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", []>; 934 //def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", []>; 935 936 } // End neverHasSideEffects 937 def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 938 def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 939 def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 940 def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 941 def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 942 def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 943 def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 944 def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>; 945 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>; 946 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 947 def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 948 def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 949 def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 950 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 951 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 952 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 953 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 954 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 955 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 956 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 957 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 958 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 959 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 960 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 961 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 962 def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 963 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 964 def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 965 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 966 def V_LSHL_B64 : VOP3_64 <0x00000161, "V_LSHL_B64", []>; 967 def V_LSHR_B64 : VOP3_64 <0x00000162, "V_LSHR_B64", []>; 968 def V_ASHR_I64 : VOP3_64 <0x00000163, "V_ASHR_I64", []>; 969 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 970 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 971 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 972 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 973 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 974 def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 975 def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 976 def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 977 def : Pat < 978 (mul VSrc_32:$src0, VReg_32:$src1), 979 (V_MUL_LO_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0) 980 >; 981 def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 982 def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 983 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 984 def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 985 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 986 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 987 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 988 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 989 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 990 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 991 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 992 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", []>; 993 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", []>; 994 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>; 995 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>; 996 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 997 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 998 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 999 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 1000 1001 def S_CSELECT_B32 : SOP2 < 1002 0x0000000a, (outs SReg_32:$dst), 1003 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1004 [(set (i32 SReg_32:$dst), (select (i1 SCCReg:$scc), 1005 SReg_32:$src0, SReg_32:$src1))] 1006 >; 1007 1008 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1009 1010 // f32 pattern for S_CSELECT_B32 1011 def : Pat < 1012 (f32 (select (i1 SCCReg:$scc), SReg_32:$src0, SReg_32:$src1)), 1013 (S_CSELECT_B32 SReg_32:$src0, SReg_32:$src1, SCCReg:$scc) 1014 >; 1015 1016 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 1017 1018 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1019 [(set SReg_64:$dst, (i64 (and SSrc_64:$src0, SSrc_64:$src1)))] 1020 >; 1021 1022 def : Pat < 1023 (i1 (and SSrc_64:$src0, SSrc_64:$src1)), 1024 (S_AND_B64 SSrc_64:$src0, SSrc_64:$src1) 1025 >; 1026 1027 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 1028 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 1029 def : Pat < 1030 (i1 (or SSrc_64:$src0, SSrc_64:$src1)), 1031 (S_OR_B64 SSrc_64:$src0, SSrc_64:$src1) 1032 >; 1033 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 1034 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", []>; 1035 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1036 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1037 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1038 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1039 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1040 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1041 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1042 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1043 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1044 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1045 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", []>; 1046 def S_LSHL_B64 : SOP2_64 <0x0000001f, "S_LSHL_B64", []>; 1047 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", []>; 1048 def S_LSHR_B64 : SOP2_64 <0x00000021, "S_LSHR_B64", []>; 1049 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", []>; 1050 def S_ASHR_I64 : SOP2_64 <0x00000023, "S_ASHR_I64", []>; 1051 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1052 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1053 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1054 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1055 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1056 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1057 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1058 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1059 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1060 1061 let isCodeGenOnly = 1, isPseudo = 1 in { 1062 1063 def LOAD_CONST : AMDGPUShaderInst < 1064 (outs GPRF32:$dst), 1065 (ins i32imm:$src), 1066 "LOAD_CONST $dst, $src", 1067 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1068 >; 1069 1070 let usesCustomInserter = 1 in { 1071 1072 def SI_WQM : InstSI < 1073 (outs), 1074 (ins), 1075 "SI_WQM", 1076 [(int_SI_wqm)] 1077 >; 1078 1079 } // end usesCustomInserter 1080 1081 // SI Psuedo instructions. These are used by the CFG structurizer pass 1082 // and should be lowered to ISA instructions prior to codegen. 1083 1084 let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1085 Uses = [EXEC], Defs = [EXEC] in { 1086 1087 let isBranch = 1, isTerminator = 1 in { 1088 1089 def SI_IF : InstSI < 1090 (outs SReg_64:$dst), 1091 (ins SReg_64:$vcc, brtarget:$target), 1092 "SI_IF $dst, $vcc, $target", 1093 [(set SReg_64:$dst, (int_SI_if SReg_64:$vcc, bb:$target))] 1094 >; 1095 1096 def SI_ELSE : InstSI < 1097 (outs SReg_64:$dst), 1098 (ins SReg_64:$src, brtarget:$target), 1099 "SI_ELSE $dst, $src, $target", 1100 [(set SReg_64:$dst, (int_SI_else SReg_64:$src, bb:$target))]> { 1101 1102 let Constraints = "$src = $dst"; 1103 } 1104 1105 def SI_LOOP : InstSI < 1106 (outs), 1107 (ins SReg_64:$saved, brtarget:$target), 1108 "SI_LOOP $saved, $target", 1109 [(int_SI_loop SReg_64:$saved, bb:$target)] 1110 >; 1111 1112 } // end isBranch = 1, isTerminator = 1 1113 1114 def SI_BREAK : InstSI < 1115 (outs SReg_64:$dst), 1116 (ins SReg_64:$src), 1117 "SI_ELSE $dst, $src", 1118 [(set SReg_64:$dst, (int_SI_break SReg_64:$src))] 1119 >; 1120 1121 def SI_IF_BREAK : InstSI < 1122 (outs SReg_64:$dst), 1123 (ins SReg_64:$vcc, SReg_64:$src), 1124 "SI_IF_BREAK $dst, $vcc, $src", 1125 [(set SReg_64:$dst, (int_SI_if_break SReg_64:$vcc, SReg_64:$src))] 1126 >; 1127 1128 def SI_ELSE_BREAK : InstSI < 1129 (outs SReg_64:$dst), 1130 (ins SReg_64:$src0, SReg_64:$src1), 1131 "SI_ELSE_BREAK $dst, $src0, $src1", 1132 [(set SReg_64:$dst, (int_SI_else_break SReg_64:$src0, SReg_64:$src1))] 1133 >; 1134 1135 def SI_END_CF : InstSI < 1136 (outs), 1137 (ins SReg_64:$saved), 1138 "SI_END_CF $saved", 1139 [(int_SI_end_cf SReg_64:$saved)] 1140 >; 1141 1142 def SI_KILL : InstSI < 1143 (outs), 1144 (ins VReg_32:$src), 1145 "SI_KIL $src", 1146 [(int_AMDGPU_kill VReg_32:$src)] 1147 >; 1148 1149 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1150 // Uses = [EXEC], Defs = [EXEC] 1151 1152 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1153 1154 def SI_INDIRECT_SRC : InstSI < 1155 (outs VReg_32:$dst, SReg_64:$temp), 1156 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1157 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1158 [] 1159 >; 1160 1161 class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1162 (outs rc:$dst, SReg_64:$temp), 1163 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1164 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1165 [] 1166 > { 1167 let Constraints = "$src = $dst"; 1168 } 1169 1170 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1171 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1172 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1173 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1174 1175 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1176 1177 } // end IsCodeGenOnly, isPseudo 1178 1179 def : Pat< 1180 (int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2), 1181 (V_CNDMASK_B32_e64 VReg_32:$src2, VReg_32:$src1, (V_CMP_GT_F32_e64 0, VReg_32:$src0)) 1182 >; 1183 1184 def : Pat < 1185 (int_AMDGPU_kilp), 1186 (SI_KILL (V_MOV_B32_e32 0xbf800000)) 1187 >; 1188 1189 /* int_SI_vs_load_input */ 1190 def : Pat< 1191 (int_SI_vs_load_input SReg_128:$tlst, IMM12bit:$attr_offset, 1192 VReg_32:$buf_idx_vgpr), 1193 (BUFFER_LOAD_FORMAT_XYZW imm:$attr_offset, 0, 1, 0, 0, 0, 1194 VReg_32:$buf_idx_vgpr, SReg_128:$tlst, 1195 0, 0, 0) 1196 >; 1197 1198 /* int_SI_export */ 1199 def : Pat < 1200 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1201 VReg_32:$src0,VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), 1202 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1203 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3) 1204 >; 1205 1206 1207 /* int_SI_sample for simple 1D texture lookup */ 1208 def : Pat < 1209 (int_SI_sample imm:$writemask, (v1i32 VReg_32:$addr), 1210 SReg_256:$rsrc, SReg_128:$sampler, imm), 1211 (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, 1212 (i32 (COPY_TO_REGCLASS VReg_32:$addr, VReg_32)), 1213 SReg_256:$rsrc, SReg_128:$sampler) 1214 >; 1215 1216 class SamplePattern<Intrinsic name, MIMG opcode, RegisterClass addr_class, 1217 ValueType addr_type> : Pat < 1218 (name imm:$writemask, (addr_type addr_class:$addr), 1219 SReg_256:$rsrc, SReg_128:$sampler, imm), 1220 (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, 1221 (EXTRACT_SUBREG addr_class:$addr, sub0), 1222 SReg_256:$rsrc, SReg_128:$sampler) 1223 >; 1224 1225 class SampleRectPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class, 1226 ValueType addr_type> : Pat < 1227 (name imm:$writemask, (addr_type addr_class:$addr), 1228 SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT), 1229 (opcode imm:$writemask, 1, 0, 0, 0, 0, 0, 0, 1230 (EXTRACT_SUBREG addr_class:$addr, sub0), 1231 SReg_256:$rsrc, SReg_128:$sampler) 1232 >; 1233 1234 class SampleArrayPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class, 1235 ValueType addr_type> : Pat < 1236 (name imm:$writemask, (addr_type addr_class:$addr), 1237 SReg_256:$rsrc, SReg_128:$sampler, TEX_ARRAY), 1238 (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, 1239 (EXTRACT_SUBREG addr_class:$addr, sub0), 1240 SReg_256:$rsrc, SReg_128:$sampler) 1241 >; 1242 1243 class SampleShadowPattern<Intrinsic name, MIMG opcode, 1244 RegisterClass addr_class, ValueType addr_type> : Pat < 1245 (name imm:$writemask, (addr_type addr_class:$addr), 1246 SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW), 1247 (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, 1248 (EXTRACT_SUBREG addr_class:$addr, sub0), 1249 SReg_256:$rsrc, SReg_128:$sampler) 1250 >; 1251 1252 class SampleShadowArrayPattern<Intrinsic name, MIMG opcode, 1253 RegisterClass addr_class, ValueType addr_type> : Pat < 1254 (name imm:$writemask, (addr_type addr_class:$addr), 1255 SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW_ARRAY), 1256 (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, 1257 (EXTRACT_SUBREG addr_class:$addr, sub0), 1258 SReg_256:$rsrc, SReg_128:$sampler) 1259 >; 1260 1261 /* int_SI_sample* for texture lookups consuming more address parameters */ 1262 multiclass SamplePatterns<RegisterClass addr_class, ValueType addr_type> { 1263 def : SamplePattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>; 1264 def : SampleRectPattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>; 1265 def : SampleArrayPattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>; 1266 def : SampleShadowPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_class, addr_type>; 1267 def : SampleShadowArrayPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_class, addr_type>; 1268 1269 def : SamplePattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_class, addr_type>; 1270 def : SampleArrayPattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_class, addr_type>; 1271 def : SampleShadowPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_class, addr_type>; 1272 def : SampleShadowArrayPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_class, addr_type>; 1273 1274 def : SamplePattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_class, addr_type>; 1275 def : SampleArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_class, addr_type>; 1276 def : SampleShadowPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_class, addr_type>; 1277 def : SampleShadowArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_class, addr_type>; 1278 } 1279 1280 defm : SamplePatterns<VReg_64, v2i32>; 1281 defm : SamplePatterns<VReg_128, v4i32>; 1282 defm : SamplePatterns<VReg_256, v8i32>; 1283 defm : SamplePatterns<VReg_512, v16i32>; 1284 1285 /********** ============================================ **********/ 1286 /********** Extraction, Insertion, Building and Casting **********/ 1287 /********** ============================================ **********/ 1288 1289 foreach Index = 0-2 in { 1290 def Extract_Element_v2i32_#Index : Extract_Element < 1291 i32, v2i32, VReg_64, Index, !cast<SubRegIndex>(sub#Index) 1292 >; 1293 def Insert_Element_v2i32_#Index : Insert_Element < 1294 i32, v2i32, VReg_32, VReg_64, Index, !cast<SubRegIndex>(sub#Index) 1295 >; 1296 1297 def Extract_Element_v2f32_#Index : Extract_Element < 1298 f32, v2f32, VReg_64, Index, !cast<SubRegIndex>(sub#Index) 1299 >; 1300 def Insert_Element_v2f32_#Index : Insert_Element < 1301 f32, v2f32, VReg_32, VReg_64, Index, !cast<SubRegIndex>(sub#Index) 1302 >; 1303 } 1304 1305 foreach Index = 0-3 in { 1306 def Extract_Element_v4i32_#Index : Extract_Element < 1307 i32, v4i32, VReg_128, Index, !cast<SubRegIndex>(sub#Index) 1308 >; 1309 def Insert_Element_v4i32_#Index : Insert_Element < 1310 i32, v4i32, VReg_32, VReg_128, Index, !cast<SubRegIndex>(sub#Index) 1311 >; 1312 1313 def Extract_Element_v4f32_#Index : Extract_Element < 1314 f32, v4f32, VReg_128, Index, !cast<SubRegIndex>(sub#Index) 1315 >; 1316 def Insert_Element_v4f32_#Index : Insert_Element < 1317 f32, v4f32, VReg_32, VReg_128, Index, !cast<SubRegIndex>(sub#Index) 1318 >; 1319 } 1320 1321 foreach Index = 0-7 in { 1322 def Extract_Element_v8i32_#Index : Extract_Element < 1323 i32, v8i32, VReg_256, Index, !cast<SubRegIndex>(sub#Index) 1324 >; 1325 def Insert_Element_v8i32_#Index : Insert_Element < 1326 i32, v8i32, VReg_32, VReg_256, Index, !cast<SubRegIndex>(sub#Index) 1327 >; 1328 1329 def Extract_Element_v8f32_#Index : Extract_Element < 1330 f32, v8f32, VReg_256, Index, !cast<SubRegIndex>(sub#Index) 1331 >; 1332 def Insert_Element_v8f32_#Index : Insert_Element < 1333 f32, v8f32, VReg_32, VReg_256, Index, !cast<SubRegIndex>(sub#Index) 1334 >; 1335 } 1336 1337 foreach Index = 0-15 in { 1338 def Extract_Element_v16i32_#Index : Extract_Element < 1339 i32, v16i32, VReg_512, Index, !cast<SubRegIndex>(sub#Index) 1340 >; 1341 def Insert_Element_v16i32_#Index : Insert_Element < 1342 i32, v16i32, VReg_32, VReg_512, Index, !cast<SubRegIndex>(sub#Index) 1343 >; 1344 1345 def Extract_Element_v16f32_#Index : Extract_Element < 1346 f32, v16f32, VReg_512, Index, !cast<SubRegIndex>(sub#Index) 1347 >; 1348 def Insert_Element_v16f32_#Index : Insert_Element < 1349 f32, v16f32, VReg_32, VReg_512, Index, !cast<SubRegIndex>(sub#Index) 1350 >; 1351 } 1352 1353 def : Vector1_Build <v1i32, VReg_32, i32, VReg_32>; 1354 def : Vector2_Build <v2i32, VReg_64, i32, VReg_32>; 1355 def : Vector2_Build <v2f32, VReg_64, f32, VReg_32>; 1356 def : Vector4_Build <v4i32, VReg_128, i32, VReg_32>; 1357 def : Vector4_Build <v4f32, VReg_128, f32, VReg_32>; 1358 def : Vector8_Build <v8i32, VReg_256, i32, VReg_32>; 1359 def : Vector8_Build <v8f32, VReg_256, f32, VReg_32>; 1360 def : Vector16_Build <v16i32, VReg_512, i32, VReg_32>; 1361 def : Vector16_Build <v16f32, VReg_512, f32, VReg_32>; 1362 1363 def : BitConvert <i32, f32, SReg_32>; 1364 def : BitConvert <i32, f32, VReg_32>; 1365 1366 def : BitConvert <f32, i32, SReg_32>; 1367 def : BitConvert <f32, i32, VReg_32>; 1368 1369 /********** =================== **********/ 1370 /********** Src & Dst modifiers **********/ 1371 /********** =================== **********/ 1372 1373 def : Pat < 1374 (int_AMDIL_clamp VReg_32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1375 (V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */), 1376 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1377 >; 1378 1379 def : Pat < 1380 (fabs VReg_32:$src), 1381 (V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */), 1382 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1383 >; 1384 1385 def : Pat < 1386 (fneg VReg_32:$src), 1387 (V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */), 1388 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */) 1389 >; 1390 1391 /********** ================== **********/ 1392 /********** Immediate Patterns **********/ 1393 /********** ================== **********/ 1394 1395 def : Pat < 1396 (i32 imm:$imm), 1397 (V_MOV_B32_e32 imm:$imm) 1398 >; 1399 1400 def : Pat < 1401 (f32 fpimm:$imm), 1402 (V_MOV_B32_e32 fpimm:$imm) 1403 >; 1404 1405 def : Pat < 1406 (i1 imm:$imm), 1407 (S_MOV_B64 imm:$imm) 1408 >; 1409 1410 def : Pat < 1411 (i64 InlineImm<i64>:$imm), 1412 (S_MOV_B64 InlineImm<i64>:$imm) 1413 >; 1414 1415 // i64 immediates aren't supported in hardware, split it into two 32bit values 1416 def : Pat < 1417 (i64 imm:$imm), 1418 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1419 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1420 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1421 >; 1422 1423 /********** ===================== **********/ 1424 /********** Interpolation Paterns **********/ 1425 /********** ===================== **********/ 1426 1427 def : Pat < 1428 (int_SI_fs_constant imm:$attr_chan, imm:$attr, M0Reg:$params), 1429 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, M0Reg:$params) 1430 >; 1431 1432 def : Pat < 1433 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, VReg_64:$ij), 1434 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG VReg_64:$ij, sub0), 1435 imm:$attr_chan, imm:$attr, M0Reg:$params), 1436 (EXTRACT_SUBREG VReg_64:$ij, sub1), 1437 imm:$attr_chan, imm:$attr, M0Reg:$params) 1438 >; 1439 1440 /********** ================== **********/ 1441 /********** Intrinsic Patterns **********/ 1442 /********** ================== **********/ 1443 1444 /* llvm.AMDGPU.pow */ 1445 /* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */ 1446 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>; 1447 1448 def : Pat < 1449 (int_AMDGPU_div VSrc_32:$src0, VSrc_32:$src1), 1450 (V_MUL_LEGACY_F32_e32 VSrc_32:$src0, (V_RCP_LEGACY_F32_e32 VSrc_32:$src1)) 1451 >; 1452 1453 def : Pat< 1454 (fdiv VSrc_32:$src0, VSrc_32:$src1), 1455 (V_MUL_F32_e32 VSrc_32:$src0, (V_RCP_F32_e32 VSrc_32:$src1)) 1456 >; 1457 1458 def : Pat < 1459 (fcos VSrc_32:$src0), 1460 (V_COS_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1461 >; 1462 1463 def : Pat < 1464 (fsin VSrc_32:$src0), 1465 (V_SIN_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1466 >; 1467 1468 def : Pat < 1469 (int_AMDGPU_cube VReg_128:$src), 1470 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1471 (V_CUBETC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), 1472 (EXTRACT_SUBREG VReg_128:$src, sub1), 1473 (EXTRACT_SUBREG VReg_128:$src, sub2), 1474 0, 0, 0, 0), sub0), 1475 (V_CUBESC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), 1476 (EXTRACT_SUBREG VReg_128:$src, sub1), 1477 (EXTRACT_SUBREG VReg_128:$src, sub2), 1478 0, 0, 0, 0), sub1), 1479 (V_CUBEMA_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), 1480 (EXTRACT_SUBREG VReg_128:$src, sub1), 1481 (EXTRACT_SUBREG VReg_128:$src, sub2), 1482 0, 0, 0, 0), sub2), 1483 (V_CUBEID_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), 1484 (EXTRACT_SUBREG VReg_128:$src, sub1), 1485 (EXTRACT_SUBREG VReg_128:$src, sub2), 1486 0, 0, 0, 0), sub3) 1487 >; 1488 1489 def : Pat < 1490 (i32 (sext (i1 SReg_64:$src0))), 1491 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), SReg_64:$src0) 1492 >; 1493 1494 // 1. Offset as 8bit DWORD immediate 1495 def : Pat < 1496 (int_SI_load_const SReg_128:$sbase, IMM8bitDWORD:$offset), 1497 (S_BUFFER_LOAD_DWORD_IMM SReg_128:$sbase, IMM8bitDWORD:$offset) 1498 >; 1499 1500 // 2. Offset loaded in an 32bit SGPR 1501 def : Pat < 1502 (int_SI_load_const SReg_128:$sbase, imm:$offset), 1503 (S_BUFFER_LOAD_DWORD_SGPR SReg_128:$sbase, (S_MOV_B32 imm:$offset)) 1504 >; 1505 1506 // 3. Offset in an 32Bit VGPR 1507 def : Pat < 1508 (int_SI_load_const SReg_128:$sbase, VReg_32:$voff), 1509 (BUFFER_LOAD_DWORD 0, 1, 0, 0, 0, 0, VReg_32:$voff, SReg_128:$sbase, 0, 0, 0) 1510 >; 1511 1512 /********** ================== **********/ 1513 /********** VOP3 Patterns **********/ 1514 /********** ================== **********/ 1515 1516 def : Pat <(f32 (fadd (fmul VSrc_32:$src0, VSrc_32:$src1), VSrc_32:$src2)), 1517 (V_MAD_F32 VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2, 1518 0, 0, 0, 0)>; 1519 1520 /********** ================== **********/ 1521 /********** SMRD Patterns **********/ 1522 /********** ================== **********/ 1523 1524 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1525 // 1. Offset as 8bit DWORD immediate 1526 def : Pat < 1527 (constant_load (SIadd64bit32bit SReg_64:$sbase, IMM8bitDWORD:$offset)), 1528 (vt (Instr_IMM SReg_64:$sbase, IMM8bitDWORD:$offset)) 1529 >; 1530 1531 // 2. Offset loaded in an 32bit SGPR 1532 def : Pat < 1533 (constant_load (SIadd64bit32bit SReg_64:$sbase, imm:$offset)), 1534 (vt (Instr_SGPR SReg_64:$sbase, (S_MOV_B32 imm:$offset))) 1535 >; 1536 1537 // 3. No offset at all 1538 def : Pat < 1539 (constant_load SReg_64:$sbase), 1540 (vt (Instr_IMM SReg_64:$sbase, 0)) 1541 >; 1542 } 1543 1544 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1545 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1546 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v16i8>; 1547 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1548 1549 /********** ====================== **********/ 1550 /********** Indirect adressing **********/ 1551 /********** ====================== **********/ 1552 1553 multiclass SI_INDIRECT_Pattern <RegisterClass rc, ValueType vt, 1554 SI_INDIRECT_DST IndDst> { 1555 // 1. Extract with offset 1556 def : Pat< 1557 (vector_extract (vt rc:$vec), 1558 (i64 (zext (i32 (add VReg_32:$idx, imm:$off)))) 1559 ), 1560 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, imm:$off)) 1561 >; 1562 1563 // 2. Extract without offset 1564 def : Pat< 1565 (vector_extract (vt rc:$vec), 1566 (i64 (zext (i32 VReg_32:$idx))) 1567 ), 1568 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, 0)) 1569 >; 1570 1571 // 3. Insert with offset 1572 def : Pat< 1573 (vector_insert (vt rc:$vec), (f32 VReg_32:$val), 1574 (i64 (zext (i32 (add VReg_32:$idx, imm:$off)))) 1575 ), 1576 (vt (IndDst (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, imm:$off, VReg_32:$val)) 1577 >; 1578 1579 // 4. Insert without offset 1580 def : Pat< 1581 (vector_insert (vt rc:$vec), (f32 VReg_32:$val), 1582 (i64 (zext (i32 VReg_32:$idx))) 1583 ), 1584 (vt (IndDst (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, 0, VReg_32:$val)) 1585 >; 1586 } 1587 1588 defm : SI_INDIRECT_Pattern <VReg_64, v2f32, SI_INDIRECT_DST_V2>; 1589 defm : SI_INDIRECT_Pattern <VReg_128, v4f32, SI_INDIRECT_DST_V4>; 1590 defm : SI_INDIRECT_Pattern <VReg_256, v8f32, SI_INDIRECT_DST_V8>; 1591 defm : SI_INDIRECT_Pattern <VReg_512, v16f32, SI_INDIRECT_DST_V16>; 1592 1593 } // End isSI predicate 1594
