1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _AU1000_H_ 20 #define _AU1000_H_ 21 #ifndef _LANGUAGE_ASSEMBLY 22 #include <linux/delay.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #include <linux/types.h> 25 #include <linux/io.h> 26 #include <linux/irq.h> 27 struct au1xxx_irqmap { 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 int im_irq; 30 int im_type; 31 int im_request; 32 }; 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #endif 35 #define MEM_STCFG0 0xB4001000 36 #define MEM_STTIME0 0xB4001004 37 #define MEM_STADDR0 0xB4001008 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define MEM_STCFG1 0xB4001010 40 #define MEM_STTIME1 0xB4001014 41 #define MEM_STADDR1 0xB4001018 42 #define MEM_STCFG2 0xB4001020 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define MEM_STTIME2 0xB4001024 45 #define MEM_STADDR2 0xB4001028 46 #define MEM_STCFG3 0xB4001030 47 #define MEM_STTIME3 0xB4001034 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define MEM_STADDR3 0xB4001038 50 #define IC0_CFG0RD 0xB0400040 51 #define IC0_CFG0SET 0xB0400040 52 #define IC0_CFG0CLR 0xB0400044 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define IC0_CFG1RD 0xB0400048 55 #define IC0_CFG1SET 0xB0400048 56 #define IC0_CFG1CLR 0xB040004C 57 #define IC0_CFG2RD 0xB0400050 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define IC0_CFG2SET 0xB0400050 60 #define IC0_CFG2CLR 0xB0400054 61 #define IC0_REQ0INT 0xB0400054 62 #define IC0_SRCRD 0xB0400058 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define IC0_SRCSET 0xB0400058 65 #define IC0_SRCCLR 0xB040005C 66 #define IC0_REQ1INT 0xB040005C 67 #define IC0_ASSIGNRD 0xB0400060 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define IC0_ASSIGNSET 0xB0400060 70 #define IC0_ASSIGNCLR 0xB0400064 71 #define IC0_WAKERD 0xB0400068 72 #define IC0_WAKESET 0xB0400068 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define IC0_WAKECLR 0xB040006C 75 #define IC0_MASKRD 0xB0400070 76 #define IC0_MASKSET 0xB0400070 77 #define IC0_MASKCLR 0xB0400074 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define IC0_RISINGRD 0xB0400078 80 #define IC0_RISINGCLR 0xB0400078 81 #define IC0_FALLINGRD 0xB040007C 82 #define IC0_FALLINGCLR 0xB040007C 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define IC0_TESTBIT 0xB0400080 85 #define IC1_CFG0RD 0xB1800040 86 #define IC1_CFG0SET 0xB1800040 87 #define IC1_CFG0CLR 0xB1800044 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define IC1_CFG1RD 0xB1800048 90 #define IC1_CFG1SET 0xB1800048 91 #define IC1_CFG1CLR 0xB180004C 92 #define IC1_CFG2RD 0xB1800050 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define IC1_CFG2SET 0xB1800050 95 #define IC1_CFG2CLR 0xB1800054 96 #define IC1_REQ0INT 0xB1800054 97 #define IC1_SRCRD 0xB1800058 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define IC1_SRCSET 0xB1800058 100 #define IC1_SRCCLR 0xB180005C 101 #define IC1_REQ1INT 0xB180005C 102 #define IC1_ASSIGNRD 0xB1800060 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define IC1_ASSIGNSET 0xB1800060 105 #define IC1_ASSIGNCLR 0xB1800064 106 #define IC1_WAKERD 0xB1800068 107 #define IC1_WAKESET 0xB1800068 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 #define IC1_WAKECLR 0xB180006C 110 #define IC1_MASKRD 0xB1800070 111 #define IC1_MASKSET 0xB1800070 112 #define IC1_MASKCLR 0xB1800074 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define IC1_RISINGRD 0xB1800078 115 #define IC1_RISINGCLR 0xB1800078 116 #define IC1_FALLINGRD 0xB180007C 117 #define IC1_FALLINGCLR 0xB180007C 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define IC1_TESTBIT 0xB1800080 120 #define INTC_INT_DISABLED 0x0 121 #define INTC_INT_RISE_EDGE 0x1 122 #define INTC_INT_FALL_EDGE 0x2 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define INTC_INT_RISE_AND_FALL_EDGE 0x3 125 #define INTC_INT_HIGH_LEVEL 0x5 126 #define INTC_INT_LOW_LEVEL 0x6 127 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 130 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 131 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32) 132 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 135 #define INTX 0xFF 136 #define SYS_BASE 0xB1900000 137 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 #define SYS_CNTRL_E1S (1 << 23) 140 #define SYS_CNTRL_T1S (1 << 20) 141 #define SYS_CNTRL_M21 (1 << 19) 142 #define SYS_CNTRL_M11 (1 << 18) 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 #define SYS_CNTRL_M01 (1 << 17) 145 #define SYS_CNTRL_C1S (1 << 16) 146 #define SYS_CNTRL_BP (1 << 14) 147 #define SYS_CNTRL_EN1 (1 << 13) 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 #define SYS_CNTRL_BT1 (1 << 12) 150 #define SYS_CNTRL_EN0 (1 << 11) 151 #define SYS_CNTRL_BT0 (1 << 10) 152 #define SYS_CNTRL_E0 (1 << 8) 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define SYS_CNTRL_E0S (1 << 7) 155 #define SYS_CNTRL_32S (1 << 5) 156 #define SYS_CNTRL_T0S (1 << 4) 157 #define SYS_CNTRL_M20 (1 << 3) 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 #define SYS_CNTRL_M10 (1 << 2) 160 #define SYS_CNTRL_M00 (1 << 1) 161 #define SYS_CNTRL_C0S (1 << 0) 162 #define SYS_TOYTRIM (SYS_BASE + 0) 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 #define SYS_TOYWRITE (SYS_BASE + 4) 165 #define SYS_TOYMATCH0 (SYS_BASE + 8) 166 #define SYS_TOYMATCH1 (SYS_BASE + 0xC) 167 #define SYS_TOYMATCH2 (SYS_BASE + 0x10) 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 #define SYS_TOYREAD (SYS_BASE + 0x40) 170 #define SYS_RTCTRIM (SYS_BASE + 0x44) 171 #define SYS_RTCWRITE (SYS_BASE + 0x48) 172 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #define SYS_RTCMATCH1 (SYS_BASE + 0x50) 175 #define SYS_RTCMATCH2 (SYS_BASE + 0x54) 176 #define SYS_RTCREAD (SYS_BASE + 0x58) 177 #define I2S_DATA 0xB1000000 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 #define I2S_DATA_MASK 0xffffff 180 #define I2S_CONFIG 0xB1000004 181 #define I2S_CONFIG_XU (1 << 25) 182 #define I2S_CONFIG_XO (1 << 24) 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 #define I2S_CONFIG_RU (1 << 23) 185 #define I2S_CONFIG_RO (1 << 22) 186 #define I2S_CONFIG_TR (1 << 21) 187 #define I2S_CONFIG_TE (1 << 20) 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 #define I2S_CONFIG_TF (1 << 19) 190 #define I2S_CONFIG_RR (1 << 18) 191 #define I2S_CONFIG_RE (1 << 17) 192 #define I2S_CONFIG_RF (1 << 16) 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 #define I2S_CONFIG_PD (1 << 11) 195 #define I2S_CONFIG_LB (1 << 10) 196 #define I2S_CONFIG_IC (1 << 9) 197 #define I2S_CONFIG_FM_BIT 7 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 200 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 201 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 202 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 #define I2S_CONFIG_TN (1 << 6) 205 #define I2S_CONFIG_RN (1 << 5) 206 #define I2S_CONFIG_SZ_BIT 0 207 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 #define I2S_CONTROL 0xB1000008 210 #define I2S_CONTROL_D (1 << 1) 211 #define I2S_CONTROL_CE (1 << 0) 212 #ifndef USB_OHCI_LEN 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 #define USB_OHCI_LEN 0x00100000 215 #endif 216 #define USBD_EP0RD 0xB0200000 217 #define USBD_EP0WR 0xB0200004 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 #define USBD_EP2WR 0xB0200008 220 #define USBD_EP3WR 0xB020000C 221 #define USBD_EP4RD 0xB0200010 222 #define USBD_EP5RD 0xB0200014 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define USBD_INTEN 0xB0200018 225 #define USBD_INTSTAT 0xB020001C 226 #define USBDEV_INT_SOF (1 << 12) 227 #define USBDEV_INT_HF_BIT 6 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 230 #define USBDEV_INT_CMPLT_BIT 0 231 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 232 #define USBD_CONFIG 0xB0200020 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define USBD_EP0CS 0xB0200024 235 #define USBD_EP2CS 0xB0200028 236 #define USBD_EP3CS 0xB020002C 237 #define USBD_EP4CS 0xB0200030 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 #define USBD_EP5CS 0xB0200034 240 #define USBDEV_CS_SU (1 << 14) 241 #define USBDEV_CS_NAK (1 << 13) 242 #define USBDEV_CS_ACK (1 << 12) 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 #define USBDEV_CS_BUSY (1 << 11) 245 #define USBDEV_CS_TSIZE_BIT 1 246 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 247 #define USBDEV_CS_STALL (1 << 0) 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 #define USBD_EP0RDSTAT 0xB0200040 250 #define USBD_EP0WRSTAT 0xB0200044 251 #define USBD_EP2WRSTAT 0xB0200048 252 #define USBD_EP3WRSTAT 0xB020004C 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define USBD_EP4RDSTAT 0xB0200050 255 #define USBD_EP5RDSTAT 0xB0200054 256 #define USBDEV_FSTAT_FLUSH (1 << 6) 257 #define USBDEV_FSTAT_UF (1 << 5) 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 #define USBDEV_FSTAT_OF (1 << 4) 260 #define USBDEV_FSTAT_FCNT_BIT 0 261 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 262 #define USBD_ENABLE 0xB0200058 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 #define USBDEV_ENABLE (1 << 1) 265 #define USBDEV_CE (1 << 0) 266 #define MAC_CONTROL 0x0 267 #define MAC_RX_ENABLE (1 << 2) 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 #define MAC_TX_ENABLE (1 << 3) 270 #define MAC_DEF_CHECK (1 << 5) 271 #define MAC_SET_BL(X) (((X) & 0x3) << 6) 272 #define MAC_AUTO_PAD (1 << 8) 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 #define MAC_DISABLE_RETRY (1 << 10) 275 #define MAC_DISABLE_BCAST (1 << 11) 276 #define MAC_LATE_COL (1 << 12) 277 #define MAC_HASH_MODE (1 << 13) 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 #define MAC_HASH_ONLY (1 << 15) 280 #define MAC_PASS_ALL (1 << 16) 281 #define MAC_INVERSE_FILTER (1 << 17) 282 #define MAC_PROMISCUOUS (1 << 18) 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 #define MAC_PASS_ALL_MULTI (1 << 19) 285 #define MAC_FULL_DUPLEX (1 << 20) 286 #define MAC_NORMAL_MODE 0 287 #define MAC_INT_LOOPBACK (1 << 21) 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define MAC_EXT_LOOPBACK (1 << 22) 290 #define MAC_DISABLE_RX_OWN (1 << 23) 291 #define MAC_BIG_ENDIAN (1 << 30) 292 #define MAC_RX_ALL (1 << 31) 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 #define MAC_ADDRESS_HIGH 0x4 295 #define MAC_ADDRESS_LOW 0x8 296 #define MAC_MCAST_HIGH 0xC 297 #define MAC_MCAST_LOW 0x10 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 #define MAC_MII_CNTRL 0x14 300 #define MAC_MII_BUSY (1 << 0) 301 #define MAC_MII_READ 0 302 #define MAC_MII_WRITE (1 << 1) 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 #define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) 305 #define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) 306 #define MAC_MII_DATA 0x18 307 #define MAC_FLOW_CNTRL 0x1C 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define MAC_FLOW_CNTRL_BUSY (1 << 0) 310 #define MAC_FLOW_CNTRL_ENABLE (1 << 1) 311 #define MAC_PASS_CONTROL (1 << 2) 312 #define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define MAC_VLAN1_TAG 0x20 315 #define MAC_VLAN2_TAG 0x24 316 #define MAC_EN_CLOCK_ENABLE (1 << 0) 317 #define MAC_EN_RESET0 (1 << 1) 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 #define MAC_EN_TOSS (0 << 2) 320 #define MAC_EN_CACHEABLE (1 << 3) 321 #define MAC_EN_RESET1 (1 << 4) 322 #define MAC_EN_RESET2 (1 << 5) 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 #define MAC_DMA_RESET (1 << 6) 325 #define MAC0_TX_DMA_ADDR 0xB4004000 326 #define MAC1_TX_DMA_ADDR 0xB4004200 327 #define MAC_TX_BUFF0_STATUS 0x0 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 #define TX_FRAME_ABORTED (1 << 0) 330 #define TX_JAB_TIMEOUT (1 << 1) 331 #define TX_NO_CARRIER (1 << 2) 332 #define TX_LOSS_CARRIER (1 << 3) 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 #define TX_EXC_DEF (1 << 4) 335 #define TX_LATE_COLL_ABORT (1 << 5) 336 #define TX_EXC_COLL (1 << 6) 337 #define TX_UNDERRUN (1 << 7) 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 #define TX_DEFERRED (1 << 8) 340 #define TX_LATE_COLL (1 << 9) 341 #define TX_COLL_CNT_MASK (0xF << 10) 342 #define TX_PKT_RETRY (1 << 31) 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 #define MAC_TX_BUFF0_ADDR 0x4 345 #define TX_DMA_ENABLE (1 << 0) 346 #define TX_T_DONE (1 << 1) 347 #define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 #define MAC_TX_BUFF0_LEN 0x8 350 #define MAC_TX_BUFF1_STATUS 0x10 351 #define MAC_TX_BUFF1_ADDR 0x14 352 #define MAC_TX_BUFF1_LEN 0x18 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 #define MAC_TX_BUFF2_STATUS 0x20 355 #define MAC_TX_BUFF2_ADDR 0x24 356 #define MAC_TX_BUFF2_LEN 0x28 357 #define MAC_TX_BUFF3_STATUS 0x30 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 #define MAC_TX_BUFF3_ADDR 0x34 360 #define MAC_TX_BUFF3_LEN 0x38 361 #define MAC0_RX_DMA_ADDR 0xB4004100 362 #define MAC1_RX_DMA_ADDR 0xB4004300 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 #define MAC_RX_BUFF0_STATUS 0x0 365 #define RX_FRAME_LEN_MASK 0x3fff 366 #define RX_WDOG_TIMER (1 << 14) 367 #define RX_RUNT (1 << 15) 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 #define RX_OVERLEN (1 << 16) 370 #define RX_COLL (1 << 17) 371 #define RX_ETHER (1 << 18) 372 #define RX_MII_ERROR (1 << 19) 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 #define RX_DRIBBLING (1 << 20) 375 #define RX_CRC_ERROR (1 << 21) 376 #define RX_VLAN1 (1 << 22) 377 #define RX_VLAN2 (1 << 23) 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 #define RX_LEN_ERROR (1 << 24) 380 #define RX_CNTRL_FRAME (1 << 25) 381 #define RX_U_CNTRL_FRAME (1 << 26) 382 #define RX_MCAST_FRAME (1 << 27) 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 #define RX_BCAST_FRAME (1 << 28) 385 #define RX_FILTER_FAIL (1 << 29) 386 #define RX_PACKET_FILTER (1 << 30) 387 #define RX_MISSED_FRAME (1 << 31) 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 390 #define MAC_RX_BUFF0_ADDR 0x4 391 #define RX_DMA_ENABLE (1 << 0) 392 #define RX_T_DONE (1 << 1) 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 #define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 395 #define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) 396 #define MAC_RX_BUFF1_STATUS 0x10 397 #define MAC_RX_BUFF1_ADDR 0x14 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 #define MAC_RX_BUFF2_STATUS 0x20 400 #define MAC_RX_BUFF2_ADDR 0x24 401 #define MAC_RX_BUFF3_STATUS 0x30 402 #define MAC_RX_BUFF3_ADDR 0x34 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 #define UART_BASE UART0_ADDR 405 #define UART_DEBUG_BASE UART3_ADDR 406 #define UART_RX 0 407 #define UART_TX 4 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 #define UART_IER 8 410 #define UART_IIR 0xC 411 #define UART_FCR 0x10 412 #define UART_LCR 0x14 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 #define UART_MCR 0x18 415 #define UART_LSR 0x1C 416 #define UART_MSR 0x20 417 #define UART_CLK 0x28 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 #define UART_MOD_CNTRL 0x100 420 #define UART_FCR_ENABLE_FIFO 0x01 421 #define UART_FCR_CLEAR_RCVR 0x02 422 #define UART_FCR_CLEAR_XMIT 0x04 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 #define UART_FCR_DMA_SELECT 0x08 425 #define UART_FCR_TRIGGER_MASK 0xF0 426 #define UART_FCR_R_TRIGGER_1 0x00 427 #define UART_FCR_R_TRIGGER_4 0x40 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 #define UART_FCR_R_TRIGGER_8 0x80 430 #define UART_FCR_R_TRIGGER_14 0xA0 431 #define UART_FCR_T_TRIGGER_0 0x00 432 #define UART_FCR_T_TRIGGER_4 0x10 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 #define UART_FCR_T_TRIGGER_8 0x20 435 #define UART_FCR_T_TRIGGER_12 0x30 436 #define UART_LCR_SBC 0x40 437 #define UART_LCR_SPAR 0x20 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 #define UART_LCR_EPAR 0x10 440 #define UART_LCR_PARITY 0x08 441 #define UART_LCR_STOP 0x04 442 #define UART_LCR_WLEN5 0x00 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 #define UART_LCR_WLEN6 0x01 445 #define UART_LCR_WLEN7 0x02 446 #define UART_LCR_WLEN8 0x03 447 #define UART_LSR_TEMT 0x40 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 #define UART_LSR_THRE 0x20 450 #define UART_LSR_BI 0x10 451 #define UART_LSR_FE 0x08 452 #define UART_LSR_PE 0x04 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 #define UART_LSR_OE 0x02 455 #define UART_LSR_DR 0x01 456 #define UART_IIR_NO_INT 0x01 457 #define UART_IIR_ID 0x06 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 #define UART_IIR_MSI 0x00 460 #define UART_IIR_THRI 0x02 461 #define UART_IIR_RDI 0x04 462 #define UART_IIR_RLSI 0x06 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 #define UART_IER_MSI 0x08 465 #define UART_IER_RLSI 0x04 466 #define UART_IER_THRI 0x02 467 #define UART_IER_RDI 0x01 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 #define UART_MCR_LOOP 0x10 470 #define UART_MCR_OUT2 0x08 471 #define UART_MCR_OUT1 0x04 472 #define UART_MCR_RTS 0x02 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 #define UART_MCR_DTR 0x01 475 #define UART_MSR_DCD 0x80 476 #define UART_MSR_RI 0x40 477 #define UART_MSR_DSR 0x20 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 #define UART_MSR_CTS 0x10 480 #define UART_MSR_DDCD 0x08 481 #define UART_MSR_TERI 0x04 482 #define UART_MSR_DDSR 0x02 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 #define UART_MSR_DCTS 0x01 485 #define UART_MSR_ANY_DELTA 0x0F 486 #define SSI0_STATUS 0xB1600000 487 #define SSI_STATUS_BF (1 << 4) 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 #define SSI_STATUS_OF (1 << 3) 490 #define SSI_STATUS_UF (1 << 2) 491 #define SSI_STATUS_D (1 << 1) 492 #define SSI_STATUS_B (1 << 0) 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 #define SSI0_INT 0xB1600004 495 #define SSI_INT_OI (1 << 3) 496 #define SSI_INT_UI (1 << 2) 497 #define SSI_INT_DI (1 << 1) 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 #define SSI0_INT_ENABLE 0xB1600008 500 #define SSI_INTE_OIE (1 << 3) 501 #define SSI_INTE_UIE (1 << 2) 502 #define SSI_INTE_DIE (1 << 1) 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 #define SSI0_CONFIG 0xB1600020 505 #define SSI_CONFIG_AO (1 << 24) 506 #define SSI_CONFIG_DO (1 << 23) 507 #define SSI_CONFIG_ALEN_BIT 20 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 #define SSI_CONFIG_ALEN_MASK (0x7 << 20) 510 #define SSI_CONFIG_DLEN_BIT 16 511 #define SSI_CONFIG_DLEN_MASK (0x7 << 16) 512 #define SSI_CONFIG_DD (1 << 11) 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 #define SSI_CONFIG_AD (1 << 10) 515 #define SSI_CONFIG_BM_BIT 8 516 #define SSI_CONFIG_BM_MASK (0x3 << 8) 517 #define SSI_CONFIG_CE (1 << 7) 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 #define SSI_CONFIG_DP (1 << 6) 520 #define SSI_CONFIG_DL (1 << 5) 521 #define SSI_CONFIG_EP (1 << 4) 522 #define SSI0_ADATA 0xB1600024 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 #define SSI_AD_D (1 << 24) 525 #define SSI_AD_ADDR_BIT 16 526 #define SSI_AD_ADDR_MASK (0xff << 16) 527 #define SSI_AD_DATA_BIT 0 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 #define SSI_AD_DATA_MASK (0xfff << 0) 530 #define SSI0_CLKDIV 0xB1600028 531 #define SSI0_CONTROL 0xB1600100 532 #define SSI_CONTROL_CD (1 << 1) 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 #define SSI_CONTROL_E (1 << 0) 535 #define SSI1_STATUS 0xB1680000 536 #define SSI1_INT 0xB1680004 537 #define SSI1_INT_ENABLE 0xB1680008 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 #define SSI1_CONFIG 0xB1680020 540 #define SSI1_ADATA 0xB1680024 541 #define SSI1_CLKDIV 0xB1680028 542 #define SSI1_ENABLE 0xB1680100 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 #define SSI_STATUS_BF (1 << 4) 545 #define SSI_STATUS_OF (1 << 3) 546 #define SSI_STATUS_UF (1 << 2) 547 #define SSI_STATUS_D (1 << 1) 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 #define SSI_STATUS_B (1 << 0) 550 #define SSI_INT_OI (1 << 3) 551 #define SSI_INT_UI (1 << 2) 552 #define SSI_INT_DI (1 << 1) 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 #define SSI_INTEN_OIE (1 << 3) 555 #define SSI_INTEN_UIE (1 << 2) 556 #define SSI_INTEN_DIE (1 << 1) 557 #define SSI_CONFIG_AO (1 << 24) 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 #define SSI_CONFIG_DO (1 << 23) 560 #define SSI_CONFIG_ALEN (7 << 20) 561 #define SSI_CONFIG_DLEN (15 << 16) 562 #define SSI_CONFIG_DD (1 << 11) 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 #define SSI_CONFIG_AD (1 << 10) 565 #define SSI_CONFIG_BM (3 << 8) 566 #define SSI_CONFIG_CE (1 << 7) 567 #define SSI_CONFIG_DP (1 << 6) 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 #define SSI_CONFIG_DL (1 << 5) 570 #define SSI_CONFIG_EP (1 << 4) 571 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20) 572 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16) 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 #define SSI_CONFIG_BM_HI (0 << 8) 575 #define SSI_CONFIG_BM_LO (1 << 8) 576 #define SSI_CONFIG_BM_CY (2 << 8) 577 #define SSI_ADATA_D (1 << 24) 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 #define SSI_ADATA_ADDR (0xFF << 16) 580 #define SSI_ADATA_DATA 0x0FFF 581 #define SSI_ADATA_ADDR_N(N) (N << 16) 582 #define SSI_ENABLE_CD (1 << 1) 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 #define SSI_ENABLE_E (1 << 0) 585 #define IRDA_BASE 0xB0300000 586 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) 587 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) 590 #define IR_RING_SIZE (IRDA_BASE + 0x0C) 591 #define IR_RING_PROMPT (IRDA_BASE + 0x10) 592 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 #define IR_INT_CLEAR (IRDA_BASE + 0x18) 595 #define IR_CONFIG_1 (IRDA_BASE + 0x20) 596 #define IR_RX_INVERT_LED (1 << 0) 597 #define IR_TX_INVERT_LED (1 << 1) 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 #define IR_ST (1 << 2) 600 #define IR_SF (1 << 3) 601 #define IR_SIR (1 << 4) 602 #define IR_MIR (1 << 5) 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 #define IR_FIR (1 << 6) 605 #define IR_16CRC (1 << 7) 606 #define IR_TD (1 << 8) 607 #define IR_RX_ALL (1 << 9) 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 #define IR_DMA_ENABLE (1 << 10) 610 #define IR_RX_ENABLE (1 << 11) 611 #define IR_TX_ENABLE (1 << 12) 612 #define IR_LOOPBACK (1 << 14) 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 615 #define IR_SIR_FLAGS (IRDA_BASE + 0x24) 616 #define IR_ENABLE (IRDA_BASE + 0x28) 617 #define IR_RX_STATUS (1 << 9) 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 #define IR_TX_STATUS (1 << 10) 620 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) 621 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) 622 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) 625 #define IR_CONFIG_2 (IRDA_BASE + 0x3C) 626 #define IR_MODE_INV (1 << 0) 627 #define IR_ONE_PIN (1 << 1) 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) 630 #define SYS_PINFUNC 0xB190002C 631 #define SYS_PF_USB (1 << 15) 632 #define SYS_PF_U3 (1 << 14) 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 #define SYS_PF_U2 (1 << 13) 635 #define SYS_PF_U1 (1 << 12) 636 #define SYS_PF_SRC (1 << 11) 637 #define SYS_PF_CK5 (1 << 10) 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 #define SYS_PF_CK4 (1 << 9) 640 #define SYS_PF_IRF (1 << 8) 641 #define SYS_PF_UR3 (1 << 7) 642 #define SYS_PF_I2D (1 << 6) 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 #define SYS_PF_I2S (1 << 5) 645 #define SYS_PF_NI2 (1 << 4) 646 #define SYS_PF_U0 (1 << 3) 647 #define SYS_PF_RD (1 << 2) 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 #define SYS_PF_A97 (1 << 1) 650 #define SYS_PF_S0 (1 << 0) 651 #define SYS_PF_PC (1 << 18) 652 #define SYS_PF_LCD (1 << 17) 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 #define SYS_PF_CS (1 << 16) 655 #define SYS_PF_EX0 (1 << 9) 656 #define SYS_PF_PSC2_MASK (7 << 17) 657 #define SYS_PF_PSC2_AC97 0 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 #define SYS_PF_PSC2_SPI 0 660 #define SYS_PF_PSC2_I2S (1 << 17) 661 #define SYS_PF_PSC2_SMBUS (3 << 17) 662 #define SYS_PF_PSC2_GPIO (7 << 17) 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 #define SYS_PF_PSC3_MASK (7 << 20) 665 #define SYS_PF_PSC3_AC97 0 666 #define SYS_PF_PSC3_SPI 0 667 #define SYS_PF_PSC3_I2S (1 << 20) 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 #define SYS_PF_PSC3_SMBUS (3 << 20) 670 #define SYS_PF_PSC3_GPIO (7 << 20) 671 #define SYS_PF_PSC1_S1 (1 << 1) 672 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 #define SYS_TRIOUTRD 0xB1900100 675 #define SYS_TRIOUTCLR 0xB1900100 676 #define SYS_OUTPUTRD 0xB1900108 677 #define SYS_OUTPUTSET 0xB1900108 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 #define SYS_OUTPUTCLR 0xB190010C 680 #define SYS_PINSTATERD 0xB1900110 681 #define SYS_PININPUTEN 0xB1900110 682 #define GPIO2_BASE 0xB1700000 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 #define GPIO2_DIR (GPIO2_BASE + 0) 685 #define GPIO2_OUTPUT (GPIO2_BASE + 8) 686 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC) 687 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10) 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 #define GPIO2_ENABLE (GPIO2_BASE + 0x14) 690 #define SYS_SCRATCH0 0xB1900018 691 #define SYS_SCRATCH1 0xB190001C 692 #define SYS_WAKEMSK 0xB1900034 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 #define SYS_ENDIAN 0xB1900038 695 #define SYS_POWERCTRL 0xB190003C 696 #define SYS_WAKESRC 0xB190005C 697 #define SYS_SLPPWR 0xB1900078 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 #define SYS_SLEEP 0xB190007C 700 #define SYS_FREQCTRL0 0xB1900020 701 #define SYS_FC_FRDIV2_BIT 22 702 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 #define SYS_FC_FE2 (1 << 21) 705 #define SYS_FC_FS2 (1 << 20) 706 #define SYS_FC_FRDIV1_BIT 12 707 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 #define SYS_FC_FE1 (1 << 11) 710 #define SYS_FC_FS1 (1 << 10) 711 #define SYS_FC_FRDIV0_BIT 2 712 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 713 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 #define SYS_FC_FE0 (1 << 1) 715 #define SYS_FC_FS0 (1 << 0) 716 #define SYS_FREQCTRL1 0xB1900024 717 #define SYS_FC_FRDIV5_BIT 22 718 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 720 #define SYS_FC_FE5 (1 << 21) 721 #define SYS_FC_FS5 (1 << 20) 722 #define SYS_FC_FRDIV4_BIT 12 723 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 725 #define SYS_FC_FE4 (1 << 11) 726 #define SYS_FC_FS4 (1 << 10) 727 #define SYS_FC_FRDIV3_BIT 2 728 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 730 #define SYS_FC_FE3 (1 << 1) 731 #define SYS_FC_FS3 (1 << 0) 732 #define SYS_CLKSRC 0xB1900028 733 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 #define SYS_CS_ME1_BIT 27 735 #define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) 736 #define SYS_CS_DE1 (1 << 26) 737 #define SYS_CS_CE1 (1 << 25) 738 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 #define SYS_CS_ME0_BIT 22 740 #define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) 741 #define SYS_CS_DE0 (1 << 21) 742 #define SYS_CS_CE0 (1 << 20) 743 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 #define SYS_CS_MI2_BIT 17 745 #define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) 746 #define SYS_CS_DI2 (1 << 16) 747 #define SYS_CS_CI2 (1 << 15) 748 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 #define SYS_CS_MUH_BIT 12 750 #define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) 751 #define SYS_CS_DUH (1 << 11) 752 #define SYS_CS_CUH (1 << 10) 753 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 #define SYS_CS_MUD_BIT 7 755 #define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) 756 #define SYS_CS_DUD (1 << 6) 757 #define SYS_CS_CUD (1 << 5) 758 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 #define SYS_CS_MIR_BIT 2 760 #define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) 761 #define SYS_CS_DIR (1 << 1) 762 #define SYS_CS_CIR (1 << 0) 763 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764 #define SYS_CS_MUX_AUX 0x1 765 #define SYS_CS_MUX_FQ0 0x2 766 #define SYS_CS_MUX_FQ1 0x3 767 #define SYS_CS_MUX_FQ2 0x4 768 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 #define SYS_CS_MUX_FQ3 0x5 770 #define SYS_CS_MUX_FQ4 0x6 771 #define SYS_CS_MUX_FQ5 0x7 772 #define SYS_CPUPLL 0xB1900060 773 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774 #define SYS_AUXPLL 0xB1900064 775 #define AC97C_CONFIG 0xB0000000 776 #define AC97C_RECV_SLOTS_BIT 13 777 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 778 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 #define AC97C_XMIT_SLOTS_BIT 3 780 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 781 #define AC97C_SG (1 << 2) 782 #define AC97C_SYNC (1 << 1) 783 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784 #define AC97C_RESET (1 << 0) 785 #define AC97C_STATUS 0xB0000004 786 #define AC97C_XU (1 << 11) 787 #define AC97C_XO (1 << 10) 788 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789 #define AC97C_RU (1 << 9) 790 #define AC97C_RO (1 << 8) 791 #define AC97C_READY (1 << 7) 792 #define AC97C_CP (1 << 6) 793 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 #define AC97C_TR (1 << 5) 795 #define AC97C_TE (1 << 4) 796 #define AC97C_TF (1 << 3) 797 #define AC97C_RR (1 << 2) 798 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799 #define AC97C_RE (1 << 1) 800 #define AC97C_RF (1 << 0) 801 #define AC97C_DATA 0xB0000008 802 #define AC97C_CMD 0xB000000C 803 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804 #define AC97C_WD_BIT 16 805 #define AC97C_READ (1 << 7) 806 #define AC97C_INDEX_MASK 0x7f 807 #define AC97C_CNTRL 0xB0000010 808 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809 #define AC97C_RS (1 << 1) 810 #define AC97C_CE (1 << 0) 811 #define SD0_XMIT_FIFO 0xB0600000 812 #define SD0_RECV_FIFO 0xB0600004 813 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814 #define SD1_XMIT_FIFO 0xB0680000 815 #define SD1_RECV_FIFO 0xB0680004 816 #define IOPORT_RESOURCE_START 0x10000000 817 #define IOPORT_RESOURCE_END 0xffffffff 818 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 #define IOMEM_RESOURCE_START 0x10000000 820 #define IOMEM_RESOURCE_END 0xffffffff 821 #define PCI_IO_START 0 822 #define PCI_IO_END 0 823 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824 #define PCI_MEM_START 0 825 #define PCI_MEM_END 0 826 #define PCI_FIRST_DEVFN 0 827 #define PCI_LAST_DEVFN 0 828 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829 #ifndef _LANGUAGE_ASSEMBLY 830 typedef volatile struct { 831 u32 toytrim; 832 u32 toywrite; 833 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834 u32 toymatch0; 835 u32 toymatch1; 836 u32 toymatch2; 837 u32 cntrctrl; 838 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839 u32 scratch0; 840 u32 scratch1; 841 u32 freqctrl0; 842 u32 freqctrl1; 843 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844 u32 clksrc; 845 u32 pinfunc; 846 u32 reserved0; 847 u32 wakemsk; 848 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849 u32 endian; 850 u32 powerctrl; 851 u32 toyread; 852 u32 rtctrim; 853 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854 u32 rtcwrite; 855 u32 rtcmatch0; 856 u32 rtcmatch1; 857 u32 rtcmatch2; 858 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859 u32 rtcread; 860 u32 wakesrc; 861 u32 cpupll; 862 u32 auxpll; 863 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864 u32 reserved1; 865 u32 reserved2; 866 u32 reserved3; 867 u32 reserved4; 868 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869 u32 slppwr; 870 u32 sleep; 871 u32 reserved5[32]; 872 u32 trioutrd; 873 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874 #define trioutclr trioutrd 875 u32 reserved6; 876 u32 outputrd; 877 #define outputset outputrd 878 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879 u32 outputclr; 880 u32 pinstaterd; 881 #define pininputen pinstaterd 882 } AU1X00_SYS; 883 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884 #endif 885 #ifndef _LANGUAGE_ASSEMBLY 886 struct cpu_spec { 887 unsigned int prid_mask; 888 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889 unsigned int prid_value; 890 char *cpu_name; 891 unsigned char cpu_od; 892 unsigned char cpu_bclk; 893 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894 unsigned char cpu_pll_wo; 895 }; 896 #endif 897 #endif 898 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899
