1 /*- 2 * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ 27 */ 28 29 /* 30 * Rewritten for Android. 31 * 32 * The ARM FPSCR is described here: 33 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/Chdfafia.html 34 */ 35 36 #ifndef _FENV_H_ 37 #define _FENV_H_ 38 39 #include <sys/types.h> 40 41 __BEGIN_DECLS 42 43 typedef __uint32_t fenv_t; 44 typedef __uint32_t fexcept_t; 45 46 /* Exception flags. */ 47 #define FE_INVALID 0x01 48 #define FE_DIVBYZERO 0x02 49 #define FE_OVERFLOW 0x04 50 #define FE_UNDERFLOW 0x08 51 #define FE_INEXACT 0x10 52 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 53 #define _FPSCR_ENABLE_SHIFT 8 54 #define _FPSCR_ENABLE_MASK (FE_ALL_EXCEPT << _FPSCR_ENABLE_SHIFT) 55 56 /* Rounding modes. */ 57 #define FE_TONEAREST 0x0 58 #define FE_UPWARD 0x1 59 #define FE_DOWNWARD 0x2 60 #define FE_TOWARDZERO 0x3 61 #define _FPSCR_RMODE_SHIFT 22 62 63 /* Default floating-point environment. */ 64 extern const fenv_t __fe_dfl_env; 65 #define FE_DFL_ENV (&__fe_dfl_env) 66 67 static __inline int fegetenv(fenv_t* __envp) { 68 fenv_t _fpscr; 69 __asm__ __volatile__("vmrs %0,fpscr" : "=r" (_fpscr)); 70 *__envp = _fpscr; 71 return 0; 72 } 73 74 static __inline int fesetenv(const fenv_t* __envp) { 75 fenv_t _fpscr = *__envp; 76 __asm__ __volatile__("vmsr fpscr,%0" : :"ri" (_fpscr)); 77 return 0; 78 } 79 80 static __inline int feclearexcept(int __excepts) { 81 fexcept_t __fpscr; 82 fegetenv(&__fpscr); 83 __fpscr &= ~__excepts; 84 fesetenv(&__fpscr); 85 return 0; 86 } 87 88 static __inline int fegetexceptflag(fexcept_t* __flagp, int __excepts) { 89 fexcept_t __fpscr; 90 fegetenv(&__fpscr); 91 *__flagp = __fpscr & __excepts; 92 return 0; 93 } 94 95 static __inline int fesetexceptflag(const fexcept_t* __flagp, int __excepts) { 96 fexcept_t __fpscr; 97 fegetenv(&__fpscr); 98 __fpscr &= ~__excepts; 99 __fpscr |= *__flagp & __excepts; 100 fesetenv(&__fpscr); 101 return 0; 102 } 103 104 static __inline int feraiseexcept(int __excepts) { 105 fexcept_t __ex = __excepts; 106 fesetexceptflag(&__ex, __excepts); 107 return 0; 108 } 109 110 static __inline int fetestexcept(int __excepts) { 111 fexcept_t __fpscr; 112 fegetenv(&__fpscr); 113 return (__fpscr & __excepts); 114 } 115 116 static __inline int fegetround(void) { 117 fenv_t _fpscr; 118 fegetenv(&_fpscr); 119 return ((_fpscr >> _FPSCR_RMODE_SHIFT) & 0x3); 120 } 121 122 static __inline int fesetround(int __round) { 123 fenv_t _fpscr; 124 fegetenv(&_fpscr); 125 _fpscr &= ~(0x3 << _FPSCR_RMODE_SHIFT); 126 _fpscr |= (__round << _FPSCR_RMODE_SHIFT); 127 fesetenv(&_fpscr); 128 return 0; 129 } 130 131 static __inline int feholdexcept(fenv_t* __envp) { 132 fenv_t __env; 133 fegetenv(&__env); 134 *__envp = __env; 135 __env &= ~(FE_ALL_EXCEPT | _FPSCR_ENABLE_MASK); 136 fesetenv(&__env); 137 return 0; 138 } 139 140 static __inline int feupdateenv(const fenv_t* __envp) { 141 fexcept_t __fpscr; 142 fegetenv(&__fpscr); 143 fesetenv(__envp); 144 feraiseexcept(__fpscr & FE_ALL_EXCEPT); 145 return 0; 146 } 147 148 #if __BSD_VISIBLE 149 150 static __inline int feenableexcept(int __mask) { 151 fenv_t __old_fpscr, __new_fpscr; 152 fegetenv(&__old_fpscr); 153 __new_fpscr = __old_fpscr | (__mask & FE_ALL_EXCEPT) << _FPSCR_ENABLE_SHIFT; 154 fesetenv(&__new_fpscr); 155 return ((__old_fpscr >> _FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT); 156 } 157 158 static __inline int fedisableexcept(int __mask) { 159 fenv_t __old_fpscr, __new_fpscr; 160 fegetenv(&__old_fpscr); 161 __new_fpscr = __old_fpscr & ~((__mask & FE_ALL_EXCEPT) << _FPSCR_ENABLE_SHIFT); 162 fesetenv(&__new_fpscr); 163 return ((__old_fpscr >> _FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT); 164 } 165 166 static __inline int fegetexcept(void) { 167 fenv_t __fpscr; 168 fegetenv(&__fpscr); 169 return ((__fpscr & _FPSCR_ENABLE_MASK) >> _FPSCR_ENABLE_SHIFT); 170 } 171 172 #endif /* __BSD_VISIBLE */ 173 174 __END_DECLS 175 176 #endif /* !_FENV_H_ */ 177
