1 /* 2 DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00 3 4 This driver was ported from Marty Conner's Tulip Etherboot driver. 5 Thanks Marty Connor (mdc (at) thinguin.org) 6 You can get Tulip driver source file from this URL: 7 8 "http://etherboot.sourceforge..net/#Distribution" 9 10 This davicom etherboot driver supports DM9009/DM9102/DM9102A/ 11 DM9102A+DM9801/DM9102A+DM9802 NICs. 12 13 This software may be used and distributed according to the terms 14 of the GNU Public License, incorporated herein by reference. 15 16 */ 17 18 /*********************************************************************/ 19 /* Revision History */ 20 /*********************************************************************/ 21 22 /* 23 19 OCT 2000 Sten 1.00 24 Different half and full duplex mode 25 Do the different programming for DM9801/DM9802 26 27 12 OCT 2000 Sten 0.90 28 This driver was ported from tulip driver and it 29 has the following difference. 30 Changed symbol tulip/TULIP to davicom/DAVICOM 31 Deleted some code that did not use in this driver. 32 Used chain-strcture to replace ring structure 33 for both TX/RX descriptor. 34 Allocated two tx descriptor. 35 According current media mode to set operating 36 register(CR6) 37 */ 38 39 40 /*********************************************************************/ 42 /* Declarations */ 43 /*********************************************************************/ 44 45 #include "etherboot.h" 46 #include "nic.h" 47 #include "pci.h" 48 #include "cards.h" 49 50 #undef DAVICOM_DEBUG 51 #undef DAVICOM_DEBUG_WHERE 52 53 #define TX_TIME_OUT 2*TICKS_PER_SEC 54 55 typedef unsigned char u8; 56 typedef signed char s8; 57 typedef unsigned short u16; 58 typedef signed short s16; 59 typedef unsigned int u32; 60 typedef signed int s32; 61 62 /* Register offsets for davicom device */ 63 enum davicom_offsets { 64 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, 65 CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58, 66 CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0 67 }; 68 69 /* EEPROM Address width definitions */ 70 #define EEPROM_ADDRLEN 6 71 #define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */ 72 /* Used to be 128, but we only need to read enough to get the MAC 73 address at bytes 20..25 */ 74 75 /* Data Read from the EEPROM */ 76 static unsigned char ee_data[EEPROM_SIZE]; 77 78 /* The EEPROM commands include the alway-set leading bit. */ 79 #define EE_WRITE_CMD (5 << addr_len) 80 #define EE_READ_CMD (6 << addr_len) 81 #define EE_ERASE_CMD (7 << addr_len) 82 83 /* EEPROM_Ctrl bits. */ 84 #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */ 85 #define EE_CS 0x01 /* EEPROM chip select. */ 86 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 87 #define EE_WRITE_0 0x01 88 #define EE_WRITE_1 0x05 89 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 90 #define EE_ENB (0x4800 | EE_CS) 91 92 /* Sten 10/11 for phyxcer */ 93 #define PHY_DATA_0 0x0 94 #define PHY_DATA_1 0x20000 95 #define MDCLKH 0x10000 96 97 /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI 98 implementations don't overrun the EEPROM clock. We add a bus 99 turn-around to insure that this remains true. */ 100 #define eeprom_delay() inl(ee_addr) 101 102 /* helpful macro if on a big_endian machine for changing byte order. 103 not strictly needed on Intel */ 104 #define le16_to_cpu(val) (val) 105 106 /* transmit and receive descriptor format */ 107 struct txdesc { 108 volatile unsigned long status; /* owner, status */ 109 unsigned long buf1sz:11, /* size of buffer 1 */ 110 buf2sz:11, /* size of buffer 2 */ 111 control:10; /* control bits */ 112 const unsigned char *buf1addr; /* buffer 1 address */ 113 const unsigned char *buf2addr; /* buffer 2 address */ 114 }; 115 116 struct rxdesc { 117 volatile unsigned long status; /* owner, status */ 118 unsigned long buf1sz:11, /* size of buffer 1 */ 119 buf2sz:11, /* size of buffer 2 */ 120 control:10; /* control bits */ 121 unsigned char *buf1addr; /* buffer 1 address */ 122 unsigned char *buf2addr; /* buffer 2 address */ 123 }; 124 125 /* Size of transmit and receive buffers */ 126 #define BUFLEN 1536 127 128 /*********************************************************************/ 129 /* Global Storage */ 130 /*********************************************************************/ 131 132 /* PCI Bus parameters */ 133 static unsigned short vendor, dev_id; 134 static unsigned long ioaddr; 135 136 /* Note: transmit and receive buffers must be longword aligned and 137 longword divisable */ 138 139 /* transmit descriptor and buffer */ 140 #define NTXD 2 141 static struct txdesc txd[NTXD] __attribute__ ((aligned(4))); 142 #ifdef USE_LOWMEM_BUFFER 143 #define txb ((char *)0x10000 - BUFLEN) 144 #else 145 static unsigned char txb[BUFLEN] __attribute__ ((aligned(4))); 146 #endif 147 148 /* receive descriptor(s) and buffer(s) */ 149 #define NRXD 4 150 static struct rxdesc rxd[NRXD] __attribute__ ((aligned(4))); 151 #ifdef USE_LOWMEM_BUFFER 152 #define rxb ((char *)0x10000 - NRXD * BUFLEN - BUFLEN) 153 #else 154 static unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4))); 155 #endif 156 static int rxd_tail; 157 static int TxPtr; 158 159 160 /*********************************************************************/ 162 /* Function Prototypes */ 163 /*********************************************************************/ 164 static void whereami(const char *str); 165 static int read_eeprom(unsigned long ioaddr, int location, int addr_len); 166 struct nic *davicom_probe(struct nic *nic, unsigned short *io_addrs, 167 struct pci_device *pci); 168 static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */ 169 static void davicom_reset(struct nic *nic); 170 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t, 171 unsigned int s, const char *p); 172 static int davicom_poll(struct nic *nic); 173 static void davicom_disable(struct nic *nic); 174 static void whereami (const char *str); 175 #ifdef DAVICOM_DEBUG 176 static void davicom_more(void); 177 #endif /* DAVICOM_DEBUG */ 178 static void davicom_wait(unsigned int nticks); 179 static int phy_read(int); 180 static void phy_write(int, u16); 181 static void phy_write_1bit(u32, u32); 182 static int phy_read_1bit(u32); 183 static void davicom_media_chk(struct nic *); 184 185 186 /*********************************************************************/ 188 /* Utility Routines */ 189 /*********************************************************************/ 190 191 static inline void whereami (const char *str) 192 { 193 #ifdef DAVICOM_DEBUG_WHERE 194 printf("%s\n", str); 195 /* sleep(2); */ 196 #endif 197 } 198 199 #ifdef DAVICOM_DEBUG 200 static void davicom_more() 201 { 202 printf("\n\n-- more --"); 203 while (!iskey()) 204 /* wait */; 205 getchar(); 206 printf("\n\n"); 207 } 208 #endif /* DAVICOM_DEBUG */ 209 210 static void davicom_wait(unsigned int nticks) 211 { 212 unsigned int to = currticks() + nticks; 213 while (currticks() < to) 214 /* wait */ ; 215 } 216 217 218 /*********************************************************************/ 220 /* For DAVICOM phyxcer register by MII interface */ 221 /*********************************************************************/ 222 /* 223 Read a word data from phy register 224 */ 225 static int phy_read(int location) 226 { 227 int i, phy_addr=1; 228 u16 phy_data; 229 u32 io_dcr9; 230 231 whereami("phy_read\n"); 232 233 io_dcr9 = ioaddr + CSR9; 234 235 /* Send 33 synchronization clock to Phy controller */ 236 for (i=0; i<34; i++) 237 phy_write_1bit(io_dcr9, PHY_DATA_1); 238 239 /* Send start command(01) to Phy */ 240 phy_write_1bit(io_dcr9, PHY_DATA_0); 241 phy_write_1bit(io_dcr9, PHY_DATA_1); 242 243 /* Send read command(10) to Phy */ 244 phy_write_1bit(io_dcr9, PHY_DATA_1); 245 phy_write_1bit(io_dcr9, PHY_DATA_0); 246 247 /* Send Phy addres */ 248 for (i=0x10; i>0; i=i>>1) 249 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); 250 251 /* Send register addres */ 252 for (i=0x10; i>0; i=i>>1) 253 phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0); 254 255 /* Skip transition state */ 256 phy_read_1bit(io_dcr9); 257 258 /* read 16bit data */ 259 for (phy_data=0, i=0; i<16; i++) { 260 phy_data<<=1; 261 phy_data|=phy_read_1bit(io_dcr9); 262 } 263 264 return phy_data; 265 } 266 267 /* 268 Write a word to Phy register 269 */ 270 static void phy_write(int location, u16 phy_data) 271 { 272 u16 i, phy_addr=1; 273 u32 io_dcr9; 274 275 whereami("phy_write\n"); 276 277 io_dcr9 = ioaddr + CSR9; 278 279 /* Send 33 synchronization clock to Phy controller */ 280 for (i=0; i<34; i++) 281 phy_write_1bit(io_dcr9, PHY_DATA_1); 282 283 /* Send start command(01) to Phy */ 284 phy_write_1bit(io_dcr9, PHY_DATA_0); 285 phy_write_1bit(io_dcr9, PHY_DATA_1); 286 287 /* Send write command(01) to Phy */ 288 phy_write_1bit(io_dcr9, PHY_DATA_0); 289 phy_write_1bit(io_dcr9, PHY_DATA_1); 290 291 /* Send Phy addres */ 292 for (i=0x10; i>0; i=i>>1) 293 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); 294 295 /* Send register addres */ 296 for (i=0x10; i>0; i=i>>1) 297 phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0); 298 299 /* written trasnition */ 300 phy_write_1bit(io_dcr9, PHY_DATA_1); 301 phy_write_1bit(io_dcr9, PHY_DATA_0); 302 303 /* Write a word data to PHY controller */ 304 for (i=0x8000; i>0; i>>=1) 305 phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0); 306 } 307 308 /* 309 Write one bit data to Phy Controller 310 */ 311 static void phy_write_1bit(u32 ee_addr, u32 phy_data) 312 { 313 whereami("phy_write_1bit\n"); 314 outl(phy_data, ee_addr); /* MII Clock Low */ 315 eeprom_delay(); 316 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ 317 eeprom_delay(); 318 outl(phy_data, ee_addr); /* MII Clock Low */ 319 eeprom_delay(); 320 } 321 322 /* 323 Read one bit phy data from PHY controller 324 */ 325 static int phy_read_1bit(u32 ee_addr) 326 { 327 int phy_data; 328 329 whereami("phy_read_1bit\n"); 330 331 outl(0x50000, ee_addr); 332 eeprom_delay(); 333 334 phy_data=(inl(ee_addr)>>19) & 0x1; 335 336 outl(0x40000, ee_addr); 337 eeprom_delay(); 338 339 return phy_data; 340 } 341 342 /* 343 DM9801/DM9802 present check and program 344 */ 345 static void HPNA_process(void) 346 { 347 348 if ( (phy_read(3) & 0xfff0) == 0xb900 ) { 349 if ( phy_read(31) == 0x4404 ) { 350 /* DM9801 present */ 351 if (phy_read(3) == 0xb901) 352 phy_write(16, 0x5); /* DM9801 E4 */ 353 else 354 phy_write(16, 0x1005); /* DM9801 E3 and others */ 355 phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000); 356 } else { 357 /* DM9802 present */ 358 phy_write(16, 0x5); 359 phy_write(25, (phy_read(25) & 0xff00) + 2); 360 } 361 } 362 } 363 364 /* 365 Sense media mode and set CR6 366 */ 367 static void davicom_media_chk(struct nic * nic) 368 { 369 unsigned long to, csr6; 370 371 csr6 = 0x00200000; /* SF */ 372 outl(csr6, ioaddr + CSR6); 373 374 if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) { 375 /* Set to 10BaseT mode for DM9009 */ 376 phy_write(0, 0); 377 } else { 378 /* For DM9102/DM9102A */ 379 to = currticks() + 2 * TICKS_PER_SEC; 380 while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to)) 381 /* wait */ ; 382 383 if ( (phy_read(1) & 0x24) == 0x24 ) { 384 if (phy_read(17) & 0xa000) 385 csr6 |= 0x00000200; /* Full Duplex mode */ 386 } else 387 csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */ 388 } 389 390 /* set the chip's operating mode */ 391 outl(csr6, ioaddr + CSR6); 392 393 /* DM9801/DM9802 present check & program */ 394 if (csr6 & 0x40000) 395 HPNA_process(); 396 } 397 398 399 /*********************************************************************/ 401 /* EEPROM Reading Code */ 402 /*********************************************************************/ 403 /* EEPROM routines adapted from the Linux Tulip Code */ 404 /* Reading a serial EEPROM is a "bit" grungy, but we work our way 405 through:->. 406 */ 407 static int read_eeprom(unsigned long ioaddr, int location, int addr_len) 408 { 409 int i; 410 unsigned short retval = 0; 411 long ee_addr = ioaddr + CSR9; 412 int read_cmd = location | EE_READ_CMD; 413 414 whereami("read_eeprom\n"); 415 416 outl(EE_ENB & ~EE_CS, ee_addr); 417 outl(EE_ENB, ee_addr); 418 419 /* Shift the read command bits out. */ 420 for (i = 4 + addr_len; i >= 0; i--) { 421 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 422 outl(EE_ENB | dataval, ee_addr); 423 eeprom_delay(); 424 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 425 eeprom_delay(); 426 } 427 outl(EE_ENB, ee_addr); 428 429 for (i = 16; i > 0; i--) { 430 outl(EE_ENB | EE_SHIFT_CLK, ee_addr); 431 eeprom_delay(); 432 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); 433 outl(EE_ENB, ee_addr); 434 eeprom_delay(); 435 } 436 437 /* Terminate the EEPROM access. */ 438 outl(EE_ENB & ~EE_CS, ee_addr); 439 return retval; 440 } 441 442 /*********************************************************************/ 444 /* davicom_init_chain - setup the tx and rx descriptors */ 445 /* Sten 10/9 */ 446 /*********************************************************************/ 447 static void davicom_init_chain(struct nic *nic) 448 { 449 int i; 450 451 /* setup the transmit descriptor */ 452 /* Sten: Set 2 TX descriptor but use one TX buffer because 453 it transmit a packet and wait complete every time. */ 454 for (i=0; i<NTXD; i++) { 455 txd[i].buf1addr = &txb[0]; /* Used same TX buffer */ 456 txd[i].buf2addr = (unsigned char *)&txd[i+1]; /* Point to Next TX desc */ 457 txd[i].buf1sz = 0; 458 txd[i].buf2sz = 0; 459 txd[i].control = 0x184; /* Begin/End/Chain */ 460 txd[i].status = 0x00000000; /* give ownership to Host */ 461 } 462 463 /* construct perfect filter frame with mac address as first match 464 and broadcast address for all others */ 465 for (i=0; i<192; i++) txb[i] = 0xFF; 466 txb[0] = nic->node_addr[0]; 467 txb[1] = nic->node_addr[1]; 468 txb[4] = nic->node_addr[2]; 469 txb[5] = nic->node_addr[3]; 470 txb[8] = nic->node_addr[4]; 471 txb[9] = nic->node_addr[5]; 472 473 /* setup receive descriptor */ 474 for (i=0; i<NRXD; i++) { 475 rxd[i].buf1addr = &rxb[i * BUFLEN]; 476 rxd[i].buf2addr = (unsigned char *)&rxd[i+1]; /* Point to Next RX desc */ 477 rxd[i].buf1sz = BUFLEN; 478 rxd[i].buf2sz = 0; /* not used */ 479 rxd[i].control = 0x4; /* Chain Structure */ 480 rxd[i].status = 0x80000000; /* give ownership to device */ 481 } 482 483 /* Chain the last descriptor to first */ 484 txd[NTXD - 1].buf2addr = (unsigned char *)&txd[0]; 485 rxd[NRXD - 1].buf2addr = (unsigned char *)&rxd[0]; 486 TxPtr = 0; 487 rxd_tail = 0; 488 } 489 490 491 /*********************************************************************/ 493 /* davicom_reset - Reset adapter */ 494 /*********************************************************************/ 495 static void davicom_reset(struct nic *nic) 496 { 497 unsigned long to; 498 u32 addr_low, addr_high; 499 500 whereami("davicom_reset\n"); 501 502 /* Stop Tx and RX */ 503 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); 504 505 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ 506 outl(0x00000001, ioaddr + CSR0); 507 508 davicom_wait(TICKS_PER_SEC); 509 510 /* TX/RX descriptor burst */ 511 outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */ 512 513 /* set up transmit and receive descriptors */ 514 davicom_init_chain(nic); /* Sten 10/9 */ 515 516 /* Point to receive descriptor */ 517 outl((unsigned long)&rxd[0], ioaddr + CSR3); 518 outl((unsigned long)&txd[0], ioaddr + CSR4); /* Sten 10/9 */ 519 520 /* According phyxcer media mode to set CR6, 521 DM9102/A phyxcer can auto-detect media mode */ 522 davicom_media_chk(nic); 523 524 /* Prepare Setup Frame Sten 10/9 */ 525 txd[TxPtr].buf1sz = 192; 526 txd[TxPtr].control = 0x024; /* SF/CE */ 527 txd[TxPtr].status = 0x80000000; /* Give ownership to device */ 528 529 /* Start Tx */ 530 outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6); 531 /* immediate transmit demand */ 532 outl(0, ioaddr + CSR1); 533 534 to = currticks() + TX_TIME_OUT; 535 while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */ 536 /* wait */ ; 537 538 if (currticks() >= to) { 539 printf ("TX Setup Timeout!\n"); 540 } 541 /* Point to next TX descriptor */ 542 TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */ 543 544 #ifdef DAVICOM_DEBUG 545 printf("txd.status = %X\n", txd.status); 546 printf("ticks = %d\n", currticks() - (to - TX_TIME_OUT)); 547 davicom_more(); 548 #endif 549 550 /* enable RX */ 551 outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6); 552 /* immediate poll demand */ 553 outl(0, ioaddr + CSR2); 554 } 555 556 557 /*********************************************************************/ 559 /* eth_transmit - Transmit a frame */ 560 /*********************************************************************/ 561 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t, 562 unsigned int s, const char *p) 563 { 564 unsigned long to; 565 566 whereami("davicom_transmit\n"); 567 568 /* Stop Tx */ 569 /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */ 570 571 /* setup ethernet header */ 572 memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */ 573 memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/ 574 txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */ 575 txb[ETH_ALEN*2+1] = t & 0xFF; 576 memcpy(&txb[ETH_HLEN], p, s); /* Frame data */ 577 578 /* setup the transmit descriptor */ 579 txd[TxPtr].buf1sz = ETH_HLEN+s; 580 txd[TxPtr].control = 0x00000184; /* LS+FS+CE */ 581 txd[TxPtr].status = 0x80000000; /* give ownership to device */ 582 583 /* immediate transmit demand */ 584 outl(0, ioaddr + CSR1); 585 586 to = currticks() + TX_TIME_OUT; 587 while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) 588 /* wait */ ; 589 590 if (currticks() >= to) { 591 printf ("TX Timeout!\n"); 592 } 593 594 /* Point to next TX descriptor */ 595 TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */ 596 597 } 598 599 /*********************************************************************/ 601 /* eth_poll - Wait for a frame */ 602 /*********************************************************************/ 603 static int davicom_poll(struct nic *nic) 604 { 605 whereami("davicom_poll\n"); 606 607 if (rxd[rxd_tail].status & 0x80000000) 608 return 0; 609 610 whereami("davicom_poll got one\n"); 611 612 nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16; 613 614 if( rxd[rxd_tail].status & 0x00008000){ 615 rxd[rxd_tail].status = 0x80000000; 616 rxd_tail++; 617 if (rxd_tail == NRXD) rxd_tail = 0; 618 return 0; 619 } 620 621 /* copy packet to working buffer */ 622 /* XXX - this copy could be avoided with a little more work 623 but for now we are content with it because the optimised 624 memcpy is quite fast */ 625 626 memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen); 627 628 /* return the descriptor and buffer to receive ring */ 629 rxd[rxd_tail].status = 0x80000000; 630 rxd_tail++; 631 if (rxd_tail == NRXD) rxd_tail = 0; 632 633 return 1; 634 } 635 636 /*********************************************************************/ 638 /* eth_disable - Disable the interface */ 639 /*********************************************************************/ 640 static void davicom_disable(struct nic *nic) 641 { 642 whereami("davicom_disable\n"); 643 644 /* disable interrupts */ 645 outl(0x00000000, ioaddr + CSR7); 646 647 /* Stop the chip's Tx and Rx processes. */ 648 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); 649 650 /* Clear the missed-packet counter. */ 651 (volatile unsigned long)inl(ioaddr + CSR8); 652 } 653 654 /*********************************************************************/ 656 /* eth_probe - Look for an adapter */ 657 /*********************************************************************/ 658 struct nic *davicom_probe(struct nic *nic, unsigned short *io_addrs, 659 struct pci_device *pci) 660 { 661 unsigned int i; 662 u32 l1, l2; 663 664 whereami("davicom_probe\n"); 665 666 if (io_addrs == 0 || *io_addrs == 0) 667 return 0; 668 669 vendor = pci->vendor; 670 dev_id = pci->dev_id; 671 ioaddr = *io_addrs; 672 673 /* wakeup chip */ 674 pcibios_write_config_dword(pci->bus, pci->devfn, 0x40, 0x00000000); 675 676 /* Stop the chip's Tx and Rx processes. */ 677 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); 678 679 /* Clear the missed-packet counter. */ 680 (volatile unsigned long)inl(ioaddr + CSR8); 681 682 /* Get MAC Address */ 683 /* read EEPROM data */ 684 for (i = 0; i < sizeof(ee_data)/2; i++) 685 ((unsigned short *)ee_data)[i] = 686 le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN)); 687 688 /* extract MAC address from EEPROM buffer */ 689 for (i=0; i<ETH_ALEN; i++) 690 nic->node_addr[i] = ee_data[20+i]; 691 692 printf("Davicom %! at ioaddr %#hX\n", nic->node_addr, ioaddr); 693 694 /* initialize device */ 695 davicom_reset(nic); 696 697 nic->reset = davicom_reset; 698 nic->poll = davicom_poll; 699 nic->transmit = davicom_transmit; 700 nic->disable = davicom_disable; 701 702 return nic; 703 } 704
