1 /* 2 * linux/include/asm-arm/cacheflush.h 3 * 4 * Copyright (C) 1999-2002 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _ASMARM_CACHEFLUSH_H 11 #define _ASMARM_CACHEFLUSH_H 12 13 #include <linux/sched.h> 14 #include <linux/mm.h> 15 16 #include <asm/glue.h> 17 #include <asm/shmparam.h> 18 19 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) 20 21 /* 22 * Cache Model 23 * =========== 24 */ 25 #undef _CACHE 26 #undef MULTI_CACHE 27 28 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 29 # ifdef _CACHE 30 # define MULTI_CACHE 1 31 # else 32 # define _CACHE v3 33 # endif 34 #endif 35 36 #if defined(CONFIG_CPU_ARM720T) 37 # ifdef _CACHE 38 # define MULTI_CACHE 1 39 # else 40 # define _CACHE v4 41 # endif 42 #endif 43 44 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ 45 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) 46 # define MULTI_CACHE 1 47 #endif 48 49 #if defined(CONFIG_CPU_ARM926T) 50 # ifdef _CACHE 51 # define MULTI_CACHE 1 52 # else 53 # define _CACHE arm926 54 # endif 55 #endif 56 57 #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100) 58 # ifdef _CACHE 59 # define MULTI_CACHE 1 60 # else 61 # define _CACHE v4wb 62 # endif 63 #endif 64 65 #if defined(CONFIG_CPU_XSCALE) 66 # ifdef _CACHE 67 # define MULTI_CACHE 1 68 # else 69 # define _CACHE xscale 70 # endif 71 #endif 72 73 #if defined(CONFIG_CPU_XSC3) 74 # ifdef _CACHE 75 # define MULTI_CACHE 1 76 # else 77 # define _CACHE xsc3 78 # endif 79 #endif 80 81 #if defined(CONFIG_CPU_V6) 82 //# ifdef _CACHE 83 # define MULTI_CACHE 1 84 //# else 85 //# define _CACHE v6 86 //# endif 87 #endif 88 89 #if !defined(_CACHE) && !defined(MULTI_CACHE) 90 #error Unknown cache maintainence model 91 #endif 92 93 /* 94 * This flag is used to indicate that the page pointed to by a pte 95 * is dirty and requires cleaning before returning it to the user. 96 */ 97 #define PG_dcache_dirty PG_arch_1 98 99 /* 100 * MM Cache Management 101 * =================== 102 * 103 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files 104 * implement these methods. 105 * 106 * Start addresses are inclusive and end addresses are exclusive; 107 * start addresses should be rounded down, end addresses up. 108 * 109 * See Documentation/cachetlb.txt for more information. 110 * Please note that the implementation of these, and the required 111 * effects are cache-type (VIVT/VIPT/PIPT) specific. 112 * 113 * flush_cache_kern_all() 114 * 115 * Unconditionally clean and invalidate the entire cache. 116 * 117 * flush_cache_user_mm(mm) 118 * 119 * Clean and invalidate all user space cache entries 120 * before a change of page tables. 121 * 122 * flush_cache_user_range(start, end, flags) 123 * 124 * Clean and invalidate a range of cache entries in the 125 * specified address space before a change of page tables. 126 * - start - user start address (inclusive, page aligned) 127 * - end - user end address (exclusive, page aligned) 128 * - flags - vma->vm_flags field 129 * 130 * coherent_kern_range(start, end) 131 * 132 * Ensure coherency between the Icache and the Dcache in the 133 * region described by start, end. If you have non-snooping 134 * Harvard caches, you need to implement this function. 135 * - start - virtual start address 136 * - end - virtual end address 137 * 138 * DMA Cache Coherency 139 * =================== 140 * 141 * dma_inv_range(start, end) 142 * 143 * Invalidate (discard) the specified virtual address range. 144 * May not write back any entries. If 'start' or 'end' 145 * are not cache line aligned, those lines must be written 146 * back. 147 * - start - virtual start address 148 * - end - virtual end address 149 * 150 * dma_clean_range(start, end) 151 * 152 * Clean (write back) the specified virtual address range. 153 * - start - virtual start address 154 * - end - virtual end address 155 * 156 * dma_flush_range(start, end) 157 * 158 * Clean and invalidate the specified virtual address range. 159 * - start - virtual start address 160 * - end - virtual end address 161 */ 162 163 struct cpu_cache_fns { 164 void (*flush_kern_all)(void); 165 void (*flush_user_all)(void); 166 void (*flush_user_range)(unsigned long, unsigned long, unsigned int); 167 168 void (*coherent_kern_range)(unsigned long, unsigned long); 169 void (*coherent_user_range)(unsigned long, unsigned long); 170 void (*flush_kern_dcache_page)(void *); 171 172 void (*dma_inv_range)(unsigned long, unsigned long); 173 void (*dma_clean_range)(unsigned long, unsigned long); 174 void (*dma_flush_range)(unsigned long, unsigned long); 175 }; 176 177 /* 178 * Select the calling method 179 */ 180 #ifdef MULTI_CACHE 181 182 extern struct cpu_cache_fns cpu_cache; 183 184 #define __cpuc_flush_kern_all cpu_cache.flush_kern_all 185 #define __cpuc_flush_user_all cpu_cache.flush_user_all 186 #define __cpuc_flush_user_range cpu_cache.flush_user_range 187 #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range 188 #define __cpuc_coherent_user_range cpu_cache.coherent_user_range 189 #define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page 190 191 /* 192 * These are private to the dma-mapping API. Do not use directly. 193 * Their sole purpose is to ensure that data held in the cache 194 * is visible to DMA, or data written by DMA to system memory is 195 * visible to the CPU. 196 */ 197 #define dmac_inv_range cpu_cache.dma_inv_range 198 #define dmac_clean_range cpu_cache.dma_clean_range 199 #define dmac_flush_range cpu_cache.dma_flush_range 200 201 #else 202 203 #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) 204 #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) 205 #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) 206 #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) 207 #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) 208 #define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page) 209 210 extern void __cpuc_flush_kern_all(void); 211 extern void __cpuc_flush_user_all(void); 212 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); 213 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); 214 extern void __cpuc_coherent_user_range(unsigned long, unsigned long); 215 extern void __cpuc_flush_dcache_page(void *); 216 217 /* 218 * These are private to the dma-mapping API. Do not use directly. 219 * Their sole purpose is to ensure that data held in the cache 220 * is visible to DMA, or data written by DMA to system memory is 221 * visible to the CPU. 222 */ 223 #define dmac_inv_range __glue(_CACHE,_dma_inv_range) 224 #define dmac_clean_range __glue(_CACHE,_dma_clean_range) 225 #define dmac_flush_range __glue(_CACHE,_dma_flush_range) 226 227 extern void dmac_inv_range(unsigned long, unsigned long); 228 extern void dmac_clean_range(unsigned long, unsigned long); 229 extern void dmac_flush_range(unsigned long, unsigned long); 230 231 #endif 232 233 /* 234 * flush_cache_vmap() is used when creating mappings (eg, via vmap, 235 * vmalloc, ioremap etc) in kernel space for pages. Since the 236 * direct-mappings of these pages may contain cached data, we need 237 * to do a full cache flush to ensure that writebacks don't corrupt 238 * data placed into these pages via the new mappings. 239 */ 240 #define flush_cache_vmap(start, end) flush_cache_all() 241 #define flush_cache_vunmap(start, end) flush_cache_all() 242 243 /* 244 * Copy user data from/to a page which is mapped into a different 245 * processes address space. Really, we want to allow our "user 246 * space" model to handle this. 247 */ 248 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 249 do { \ 250 memcpy(dst, src, len); \ 251 flush_ptrace_access(vma, page, vaddr, dst, len, 1);\ 252 } while (0) 253 254 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 255 do { \ 256 memcpy(dst, src, len); \ 257 } while (0) 258 259 /* 260 * Convert calls to our calling convention. 261 */ 262 #define flush_cache_all() __cpuc_flush_kern_all() 263 #ifndef CONFIG_CPU_CACHE_VIPT 264 static inline void flush_cache_mm(struct mm_struct *mm) 265 { 266 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) 267 __cpuc_flush_user_all(); 268 } 269 270 static inline void 271 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 272 { 273 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) 274 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), 275 vma->vm_flags); 276 } 277 278 static inline void 279 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) 280 { 281 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { 282 unsigned long addr = user_addr & PAGE_MASK; 283 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); 284 } 285 } 286 287 static inline void 288 flush_ptrace_access(struct vm_area_struct *vma, struct page *page, 289 unsigned long uaddr, void *kaddr, 290 unsigned long len, int write) 291 { 292 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { 293 unsigned long addr = (unsigned long)kaddr; 294 __cpuc_coherent_kern_range(addr, addr + len); 295 } 296 } 297 #else 298 extern void flush_cache_mm(struct mm_struct *mm); 299 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 300 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); 301 extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, 302 unsigned long uaddr, void *kaddr, 303 unsigned long len, int write); 304 #endif 305 306 /* 307 * flush_cache_user_range is used when we want to ensure that the 308 * Harvard caches are synchronised for the user space address range. 309 * This is used for the ARM private sys_cacheflush system call. 310 */ 311 #define flush_cache_user_range(vma,start,end) \ 312 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) 313 314 /* 315 * Perform necessary cache operations to ensure that data previously 316 * stored within this range of addresses can be executed by the CPU. 317 */ 318 #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e) 319 320 /* 321 * Perform necessary cache operations to ensure that the TLB will 322 * see data written in the specified area. 323 */ 324 #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) 325 326 /* 327 * flush_dcache_page is used when the kernel has written to the page 328 * cache page at virtual address page->virtual. 329 * 330 * If this page isn't mapped (ie, page_mapping == NULL), or it might 331 * have userspace mappings, then we _must_ always clean + invalidate 332 * the dcache entries associated with the kernel mapping. 333 * 334 * Otherwise we can defer the operation, and clean the cache when we are 335 * about to change to user space. This is the same method as used on SPARC64. 336 * See update_mmu_cache for the user space part. 337 */ 338 extern void flush_dcache_page(struct page *); 339 340 #define flush_dcache_mmap_lock(mapping) \ 341 write_lock_irq(&(mapping)->tree_lock) 342 #define flush_dcache_mmap_unlock(mapping) \ 343 write_unlock_irq(&(mapping)->tree_lock) 344 345 #define flush_icache_user_range(vma,page,addr,len) \ 346 flush_dcache_page(page) 347 348 /* 349 * We don't appear to need to do anything here. In fact, if we did, we'd 350 * duplicate cache flushing elsewhere performed by flush_dcache_page(). 351 */ 352 #define flush_icache_page(vma,page) do { } while (0) 353 354 #define __cacheid_present(val) (val != read_cpuid(CPUID_ID)) 355 #define __cacheid_vivt(val) ((val & (15 << 25)) != (14 << 25)) 356 #define __cacheid_vipt(val) ((val & (15 << 25)) == (14 << 25)) 357 #define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25)) 358 #define __cacheid_vipt_aliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23)) 359 360 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT) 361 362 #define cache_is_vivt() 1 363 #define cache_is_vipt() 0 364 #define cache_is_vipt_nonaliasing() 0 365 #define cache_is_vipt_aliasing() 0 366 367 #elif defined(CONFIG_CPU_CACHE_VIPT) 368 369 #define cache_is_vivt() 0 370 #define cache_is_vipt() 1 371 #define cache_is_vipt_nonaliasing() \ 372 ({ \ 373 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ 374 __cacheid_vipt_nonaliasing(__val); \ 375 }) 376 377 #define cache_is_vipt_aliasing() \ 378 ({ \ 379 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ 380 __cacheid_vipt_aliasing(__val); \ 381 }) 382 383 #else 384 385 #define cache_is_vivt() \ 386 ({ \ 387 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ 388 (!__cacheid_present(__val)) || __cacheid_vivt(__val); \ 389 }) 390 391 #define cache_is_vipt() \ 392 ({ \ 393 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ 394 __cacheid_present(__val) && __cacheid_vipt(__val); \ 395 }) 396 397 #define cache_is_vipt_nonaliasing() \ 398 ({ \ 399 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ 400 __cacheid_present(__val) && \ 401 __cacheid_vipt_nonaliasing(__val); \ 402 }) 403 404 #define cache_is_vipt_aliasing() \ 405 ({ \ 406 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ 407 __cacheid_present(__val) && \ 408 __cacheid_vipt_aliasing(__val); \ 409 }) 410 411 #endif 412 413 #endif 414
