1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is the top level entry point for the PowerPC target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Get the target-independent interfaces which we are implementing. 15 // 16 include "llvm/Target/Target.td" 17 18 //===----------------------------------------------------------------------===// 19 // PowerPC Subtarget features. 20 // 21 22 //===----------------------------------------------------------------------===// 23 // CPU Directives // 24 //===----------------------------------------------------------------------===// 25 26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", 39 "PPC::DIR_E500mc", "">; 40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", 41 "PPC::DIR_E5500", "">; 42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; 43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; 44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; 45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; 46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; 47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; 48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; 49 50 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 51 "Enable 64-bit instructions">; 52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 53 "Enable 64-bit registers usage for ppc32 [beta]">; 54 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 55 "Enable Altivec instructions">; 56 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 57 "Enable the MFOCRF instruction">; 58 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 59 "Enable the fsqrt instruction">; 60 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 61 "Enable the stfiwx instruction">; 62 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 63 "Enable the isel instruction">; 64 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 65 "Enable Book E instructions">; 66 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 67 "Enable QPX instructions">; 68 69 // Note: Future features to add when support is extended to more 70 // recent ISA levels: 71 // 72 // CMPB p6, p6x, p7 cmpb 73 // DFP p6, p6x, p7 decimal floating-point instructions 74 // FLT_CVT p7 fcfids, fcfidu, fcfidus, fcfiduz, fctiwuz 75 // FPRND p5x, p6, p6x, p7 frim, frin, frip, friz 76 // FRE p5 through p7 fre (vs. fres, available since p3) 77 // FRSQRTES p5 through p7 frsqrtes (vs. frsqrte, available since p3) 78 // LDBRX p7 load with byte reversal 79 // LFIWAX p6, p6x, p7 lfiwax 80 // LFIWZX p7 lfiwzx 81 // POPCNTB p5 through p7 popcntb and related instructions 82 // POPCNTD p7 popcntd and related instructions 83 // RECIP_PREC p6, p6x, p7 higher precision reciprocal estimates 84 // VSX p7 vector-scalar instruction set 85 86 //===----------------------------------------------------------------------===// 87 // Register File Description 88 //===----------------------------------------------------------------------===// 89 90 include "PPCRegisterInfo.td" 91 include "PPCSchedule.td" 92 include "PPCInstrInfo.td" 93 94 //===----------------------------------------------------------------------===// 95 // PowerPC processors supported. 96 // 97 98 def : Processor<"generic", G3Itineraries, [Directive32]>; 99 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL, 100 FeatureBookE]>; 101 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL, 102 FeatureBookE]>; 103 def : Processor<"601", G3Itineraries, [Directive601]>; 104 def : Processor<"602", G3Itineraries, [Directive602]>; 105 def : Processor<"603", G3Itineraries, [Directive603]>; 106 def : Processor<"603e", G3Itineraries, [Directive603]>; 107 def : Processor<"603ev", G3Itineraries, [Directive603]>; 108 def : Processor<"604", G3Itineraries, [Directive604]>; 109 def : Processor<"604e", G3Itineraries, [Directive604]>; 110 def : Processor<"620", G3Itineraries, [Directive620]>; 111 def : Processor<"750", G4Itineraries, [Directive750]>; 112 def : Processor<"g3", G3Itineraries, [Directive750]>; 113 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>; 114 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>; 115 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>; 116 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>; 117 def : Processor<"970", G5Itineraries, 118 [Directive970, FeatureAltivec, 119 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 120 Feature64Bit /*, Feature64BitRegs */]>; 121 def : Processor<"g5", G5Itineraries, 122 [Directive970, FeatureAltivec, 123 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 124 Feature64Bit /*, Feature64BitRegs */]>; 125 def : ProcessorModel<"e500mc", PPCE500mcModel, 126 [DirectiveE500mc, FeatureMFOCRF, 127 FeatureSTFIWX, FeatureBookE, FeatureISEL]>; 128 def : ProcessorModel<"e5500", PPCE5500Model, 129 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 130 FeatureSTFIWX, FeatureBookE, FeatureISEL]>; 131 def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE, 132 FeatureMFOCRF, FeatureFSqrt, 133 FeatureSTFIWX, FeatureISEL, 134 Feature64Bit 135 /*, Feature64BitRegs */]>; 136 def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE, 137 FeatureMFOCRF, FeatureFSqrt, 138 FeatureSTFIWX, FeatureISEL, 139 Feature64Bit /*, Feature64BitRegs */, 140 FeatureQPX]>; 141 def : Processor<"pwr3", G5Itineraries, 142 [DirectivePwr3, FeatureAltivec, FeatureMFOCRF, 143 FeatureSTFIWX, Feature64Bit]>; 144 def : Processor<"pwr4", G5Itineraries, 145 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 146 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>; 147 def : Processor<"pwr5", G5Itineraries, 148 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 149 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>; 150 def : Processor<"pwr5x", G5Itineraries, 151 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 152 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>; 153 def : Processor<"pwr6", G5Itineraries, 154 [DirectivePwr6, FeatureAltivec, 155 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 156 Feature64Bit /*, Feature64BitRegs */]>; 157 def : Processor<"pwr6x", G5Itineraries, 158 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 159 FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>; 160 def : Processor<"pwr7", G5Itineraries, 161 [DirectivePwr7, FeatureAltivec, 162 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 163 FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>; 164 def : Processor<"ppc", G3Itineraries, [Directive32]>; 165 def : Processor<"ppc64", G5Itineraries, 166 [Directive64, FeatureAltivec, 167 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 168 Feature64Bit /*, Feature64BitRegs */]>; 169 170 171 //===----------------------------------------------------------------------===// 172 // Calling Conventions 173 //===----------------------------------------------------------------------===// 174 175 include "PPCCallingConv.td" 176 177 def PPCInstrInfo : InstrInfo { 178 let isLittleEndianEncoding = 1; 179 } 180 181 def PPCAsmWriter : AsmWriter { 182 string AsmWriterClassName = "InstPrinter"; 183 bit isMCAsmWriter = 1; 184 } 185 186 def PPC : Target { 187 // Information about the instructions. 188 let InstructionSet = PPCInstrInfo; 189 190 let AssemblyWriters = [PPCAsmWriter]; 191 } 192
