1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the PowerPC 64-bit instructions. These patterns are used 11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // 64-bit operands. 17 // 18 def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 } 21 def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23 } 24 def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27 } 28 def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31 } 32 def tocentry : Operand<iPTR> { 33 let MIOperandInfo = (ops i32imm:$imm); 34 } 35 def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64 36 let PrintMethod = "printMemRegImm"; 37 let EncoderMethod = "getMemRIXEncoding"; 38 let MIOperandInfo = (ops symbolLo64:$off, ptr_rc:$reg); 39 } 40 def tlsreg : Operand<i64> { 41 let EncoderMethod = "getTLSRegEncoding"; 42 } 43 def tlsgd : Operand<i64> {} 44 45 //===----------------------------------------------------------------------===// 46 // 64-bit transformation functions. 47 // 48 49 def SHL64 : SDNodeXForm<imm, [{ 50 // Transformation function: 63 - imm 51 return getI32Imm(63 - N->getZExtValue()); 52 }]>; 53 54 def SRL64 : SDNodeXForm<imm, [{ 55 // Transformation function: 64 - imm 56 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 57 }]>; 58 59 def HI32_48 : SDNodeXForm<imm, [{ 60 // Transformation function: shift the immediate value down into the low bits. 61 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 62 }]>; 63 64 def HI48_64 : SDNodeXForm<imm, [{ 65 // Transformation function: shift the immediate value down into the low bits. 66 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 67 }]>; 68 69 70 //===----------------------------------------------------------------------===// 71 // Calls. 72 // 73 74 let Defs = [LR8] in 75 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 76 PPC970_Unit_BRU; 77 78 // Darwin ABI Calls. 79 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 80 // Convenient aliases for call instructions 81 let Uses = [RM] in { 82 def BL8_Darwin : IForm<18, 0, 1, 83 (outs), (ins calltarget:$func), 84 "bl $func", BrB, []>; // See Pat patterns below. 85 def BLA8_Darwin : IForm<18, 1, 1, 86 (outs), (ins aaddr:$func), 87 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 88 } 89 let Uses = [CTR8, RM] in { 90 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 91 (outs), (ins), 92 "bctrl", BrB, 93 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 94 } 95 } 96 97 // ELF 64 ABI Calls = Darwin ABI Calls 98 // Used to define BL8_ELF and BLA8_ELF 99 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 100 // Convenient aliases for call instructions 101 let Uses = [RM] in { 102 def BL8_ELF : IForm<18, 0, 1, 103 (outs), (ins calltarget:$func), 104 "bl $func", BrB, []>; // See Pat patterns below. 105 106 let isCodeGenOnly = 1 in 107 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24, 108 (outs), (ins calltarget:$func), 109 "bl $func\n\tnop", BrB, []>; 110 111 let isCodeGenOnly = 1 in 112 def BL8_NOP_ELF_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24, 113 (outs), (ins calltarget:$func, tlsgd:$sym), 114 "bl $func($sym)\n\tnop", BrB, []>; 115 116 let isCodeGenOnly = 1 in 117 def BL8_NOP_ELF_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24, 118 (outs), (ins calltarget:$func, tlsgd:$sym), 119 "bl $func($sym)\n\tnop", BrB, []>; 120 121 def BLA8_ELF : IForm<18, 1, 1, 122 (outs), (ins aaddr:$func), 123 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 124 125 let isCodeGenOnly = 1 in 126 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24, 127 (outs), (ins aaddr:$func), 128 "bla $func\n\tnop", BrB, 129 [(PPCcall_nop_SVR4 (i64 imm:$func))]>; 130 } 131 let Uses = [X11, CTR8, RM] in { 132 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 133 (outs), (ins), 134 "bctrl", BrB, 135 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 136 } 137 } 138 139 140 // Calls 141 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 142 (BL8_Darwin tglobaladdr:$dst)>; 143 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 144 (BL8_Darwin texternalsym:$dst)>; 145 146 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 147 (BL8_ELF tglobaladdr:$dst)>; 148 def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)), 149 (BL8_NOP_ELF tglobaladdr:$dst)>; 150 151 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 152 (BL8_ELF texternalsym:$dst)>; 153 def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)), 154 (BL8_NOP_ELF texternalsym:$dst)>; 155 156 def : Pat<(PPCnop), 157 (NOP)>; 158 159 // Atomic operations 160 let usesCustomInserter = 1 in { 161 let Defs = [CR0] in { 162 def ATOMIC_LOAD_ADD_I64 : Pseudo< 163 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64", 164 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 165 def ATOMIC_LOAD_SUB_I64 : Pseudo< 166 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64", 167 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 168 def ATOMIC_LOAD_OR_I64 : Pseudo< 169 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64", 170 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 171 def ATOMIC_LOAD_XOR_I64 : Pseudo< 172 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64", 173 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 174 def ATOMIC_LOAD_AND_I64 : Pseudo< 175 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64", 176 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 177 def ATOMIC_LOAD_NAND_I64 : Pseudo< 178 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64", 179 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 180 181 def ATOMIC_CMP_SWAP_I64 : Pseudo< 182 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64", 183 [(set G8RC:$dst, 184 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 185 186 def ATOMIC_SWAP_I64 : Pseudo< 187 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64", 188 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 189 } 190 } 191 192 // Instructions to support atomic operations 193 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 194 "ldarx $rD, $ptr", LdStLDARX, 195 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 196 197 let Defs = [CR0] in 198 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 199 "stdcx. $rS, $dst", LdStSTDCX, 200 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 201 isDOT; 202 203 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 204 def TCRETURNdi8 :Pseudo< (outs), 205 (ins calltarget:$dst, i32imm:$offset), 206 "#TC_RETURNd8 $dst $offset", 207 []>; 208 209 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 210 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 211 "#TC_RETURNa8 $func $offset", 212 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 213 214 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 215 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 216 "#TC_RETURNr8 $dst $offset", 217 []>; 218 219 220 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 221 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 222 let isReturn = 1 in { 223 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 224 Requires<[In64BitMode]>; 225 } 226 227 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 228 Requires<[In64BitMode]>; 229 } 230 231 232 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 233 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 234 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 235 "b $dst", BrB, 236 []>; 237 238 239 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 240 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 241 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 242 "ba $dst", BrB, 243 []>; 244 245 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 246 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 247 248 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 249 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 250 251 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 252 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 253 254 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 255 let Defs = [CTR8], Uses = [CTR8] in { 256 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 257 "bdz $dst">; 258 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 259 "bdnz $dst">; 260 } 261 } 262 263 // 64-but CR instructions 264 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), 265 "mtcrf $FXM, $rS", BrMCRX>, 266 PPC970_MicroCode, PPC970_Unit_CRU; 267 268 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), 269 "#MFCR8pseud", SprMFCR>, 270 PPC970_MicroCode, PPC970_Unit_CRU; 271 272 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), 273 "mfcr $rT", SprMFCR>, 274 PPC970_MicroCode, PPC970_Unit_CRU; 275 276 //===----------------------------------------------------------------------===// 277 // 64-bit SPR manipulation instrs. 278 279 let Uses = [CTR8] in { 280 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 281 "mfctr $rT", SprMFSPR>, 282 PPC970_DGroup_First, PPC970_Unit_FXU; 283 } 284 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 285 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 286 "mtctr $rS", SprMTSPR>, 287 PPC970_DGroup_First, PPC970_Unit_FXU; 288 } 289 290 let Pattern = [(set G8RC:$rT, readcyclecounter)] in 291 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins), 292 "mfspr $rT, 268", SprMFTB>, 293 PPC970_DGroup_First, PPC970_Unit_FXU; 294 // Note that encoding mftb using mfspr is now the preferred form, 295 // and has been since at least ISA v2.03. The mftb instruction has 296 // now been phased out. Using mfspr, however, is known not to work on 297 // the POWER3. 298 299 let Defs = [X1], Uses = [X1] in 300 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8", 301 [(set G8RC:$result, 302 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 303 304 let Defs = [LR8] in { 305 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 306 "mtlr $rS", SprMTSPR>, 307 PPC970_DGroup_First, PPC970_Unit_FXU; 308 } 309 let Uses = [LR8] in { 310 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 311 "mflr $rT", SprMFSPR>, 312 PPC970_DGroup_First, PPC970_Unit_FXU; 313 } 314 315 //===----------------------------------------------------------------------===// 316 // Fixed point instructions. 317 // 318 319 let PPC970_Unit = 1 in { // FXU Operations. 320 321 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 322 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 323 "li $rD, $imm", IntSimple, 324 [(set G8RC:$rD, immSExt16:$imm)]>; 325 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 326 "lis $rD, $imm", IntSimple, 327 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 328 } 329 330 // Logical ops. 331 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 332 "nand $rA, $rS, $rB", IntSimple, 333 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 334 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 335 "and $rA, $rS, $rB", IntSimple, 336 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 337 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 338 "andc $rA, $rS, $rB", IntSimple, 339 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 340 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 341 "or $rA, $rS, $rB", IntSimple, 342 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 343 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 344 "nor $rA, $rS, $rB", IntSimple, 345 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 346 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 347 "orc $rA, $rS, $rB", IntSimple, 348 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 349 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 350 "eqv $rA, $rS, $rB", IntSimple, 351 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 352 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 353 "xor $rA, $rS, $rB", IntSimple, 354 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 355 356 // Logical ops with immediate. 357 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 358 "andi. $dst, $src1, $src2", IntGeneral, 359 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 360 isDOT; 361 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 362 "andis. $dst, $src1, $src2", IntGeneral, 363 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 364 isDOT; 365 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 366 "ori $dst, $src1, $src2", IntSimple, 367 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 368 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 369 "oris $dst, $src1, $src2", IntSimple, 370 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 371 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 372 "xori $dst, $src1, $src2", IntSimple, 373 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 374 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 375 "xoris $dst, $src1, $src2", IntSimple, 376 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 377 378 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 379 "add $rT, $rA, $rB", IntSimple, 380 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 381 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 382 // initial-exec thread-local storage model. 383 def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB), 384 "add $rT, $rA, $rB@tls", IntSimple, 385 [(set G8RC:$rT, (add G8RC:$rA, tglobaltlsaddr:$rB))]>; 386 387 let Defs = [CARRY] in { 388 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 389 "addc $rT, $rA, $rB", IntGeneral, 390 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 391 PPC970_DGroup_Cracked; 392 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 393 "addic $rD, $rA, $imm", IntGeneral, 394 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 395 } 396 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 397 "addi $rD, $rA, $imm", IntSimple, 398 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 399 def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, symbolLo64:$imm), 400 "addi $rD, $rA, $imm", IntSimple, 401 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 402 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 403 "addis $rD, $rA, $imm", IntSimple, 404 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 405 406 let Defs = [CARRY] in { 407 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 408 "subfic $rD, $rA, $imm", IntGeneral, 409 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 410 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 411 "subfc $rT, $rA, $rB", IntGeneral, 412 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 413 PPC970_DGroup_Cracked; 414 } 415 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 416 "subf $rT, $rA, $rB", IntGeneral, 417 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 418 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 419 "neg $rT, $rA", IntSimple, 420 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 421 let Uses = [CARRY], Defs = [CARRY] in { 422 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 423 "adde $rT, $rA, $rB", IntGeneral, 424 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 425 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 426 "addme $rT, $rA", IntGeneral, 427 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 428 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 429 "addze $rT, $rA", IntGeneral, 430 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 431 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 432 "subfe $rT, $rA, $rB", IntGeneral, 433 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 434 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 435 "subfme $rT, $rA", IntGeneral, 436 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 437 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 438 "subfze $rT, $rA", IntGeneral, 439 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 440 } 441 442 443 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 444 "mulhd $rT, $rA, $rB", IntMulHW, 445 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 446 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 447 "mulhdu $rT, $rA, $rB", IntMulHWU, 448 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 449 450 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 451 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 452 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 453 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 454 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 455 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 456 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 457 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 458 459 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 460 "sld $rA, $rS, $rB", IntRotateD, 461 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 462 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 463 "srd $rA, $rS, $rB", IntRotateD, 464 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 465 let Defs = [CARRY] in { 466 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 467 "srad $rA, $rS, $rB", IntRotateD, 468 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 469 } 470 471 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 472 "extsb $rA, $rS", IntSimple, 473 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 474 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 475 "extsh $rA, $rS", IntSimple, 476 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 477 478 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 479 "extsw $rA, $rS", IntSimple, 480 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 481 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 482 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 483 "extsw $rA, $rS", IntSimple, 484 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 485 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 486 "extsw $rA, $rS", IntSimple, 487 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 488 489 let Defs = [CARRY] in { 490 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 491 "sradi $rA, $rS, $SH", IntRotateDI, 492 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 493 } 494 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 495 "cntlzd $rA, $rS", IntGeneral, 496 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 497 498 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 499 "divd $rT, $rA, $rB", IntDivD, 500 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 501 PPC970_DGroup_First, PPC970_DGroup_Cracked; 502 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 503 "divdu $rT, $rA, $rB", IntDivD, 504 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 505 PPC970_DGroup_First, PPC970_DGroup_Cracked; 506 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 507 "mulld $rT, $rA, $rB", IntMulHD, 508 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 509 510 511 let isCommutable = 1 in { 512 def RLDIMI : MDForm_1<30, 3, 513 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 514 "rldimi $rA, $rS, $SH, $MB", IntRotateDI, 515 []>, isPPC64, RegConstraint<"$rSi = $rA">, 516 NoEncode<"$rSi">; 517 } 518 519 // Rotate instructions. 520 def RLDCL : MDForm_1<30, 0, 521 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE), 522 "rldcl $rA, $rS, $rB, $MBE", IntRotateD, 523 []>, isPPC64; 524 def RLDICL : MDForm_1<30, 0, 525 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 526 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI, 527 []>, isPPC64; 528 def RLDICR : MDForm_1<30, 1, 529 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 530 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI, 531 []>, isPPC64; 532 533 def RLWINM8 : MForm_2<21, 534 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 535 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 536 []>; 537 538 def ISEL8 : AForm_4<31, 15, 539 (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB, pred:$cond), 540 "isel $rT, $rA, $rB, $cond", IntGeneral, 541 []>; 542 } // End FXU Operations. 543 544 545 //===----------------------------------------------------------------------===// 546 // Load/Store instructions. 547 // 548 549 550 // Sign extending loads. 551 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 552 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 553 "lha $rD, $src", LdStLHA, 554 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 555 PPC970_DGroup_Cracked; 556 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 557 "lwa $rD, $src", LdStLWA, 558 [(set G8RC:$rD, 559 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 560 PPC970_DGroup_Cracked; 561 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 562 "lhax $rD, $src", LdStLHA, 563 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 564 PPC970_DGroup_Cracked; 565 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 566 "lwax $rD, $src", LdStLHA, 567 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 568 PPC970_DGroup_Cracked; 569 570 // Update forms. 571 let mayLoad = 1 in 572 def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 573 ptr_rc:$rA), 574 "lhau $rD, $disp($rA)", LdStLHAU, 575 []>, RegConstraint<"$rA = $ea_result">, 576 NoEncode<"$ea_result">; 577 // NO LWAU! 578 579 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result), 580 (ins memrr:$addr), 581 "lhaux $rD, $addr", LdStLHAU, 582 []>, RegConstraint<"$addr.offreg = $ea_result">, 583 NoEncode<"$ea_result">; 584 def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc:$ea_result), 585 (ins memrr:$addr), 586 "lwaux $rD, $addr", LdStLHAU, 587 []>, RegConstraint<"$addr.offreg = $ea_result">, 588 NoEncode<"$ea_result">, isPPC64; 589 } 590 591 // Zero extending loads. 592 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 593 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 594 "lbz $rD, $src", LdStLoad, 595 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 596 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 597 "lhz $rD, $src", LdStLoad, 598 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 599 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 600 "lwz $rD, $src", LdStLoad, 601 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 602 603 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 604 "lbzx $rD, $src", LdStLoad, 605 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 606 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 607 "lhzx $rD, $src", LdStLoad, 608 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 609 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 610 "lwzx $rD, $src", LdStLoad, 611 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 612 613 614 // Update forms. 615 let mayLoad = 1 in { 616 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 617 "lbzu $rD, $addr", LdStLoadUpd, 618 []>, RegConstraint<"$addr.reg = $ea_result">, 619 NoEncode<"$ea_result">; 620 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 621 "lhzu $rD, $addr", LdStLoadUpd, 622 []>, RegConstraint<"$addr.reg = $ea_result">, 623 NoEncode<"$ea_result">; 624 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 625 "lwzu $rD, $addr", LdStLoadUpd, 626 []>, RegConstraint<"$addr.reg = $ea_result">, 627 NoEncode<"$ea_result">; 628 629 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc:$ea_result), 630 (ins memrr:$addr), 631 "lbzux $rD, $addr", LdStLoadUpd, 632 []>, RegConstraint<"$addr.offreg = $ea_result">, 633 NoEncode<"$ea_result">; 634 def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc:$ea_result), 635 (ins memrr:$addr), 636 "lhzux $rD, $addr", LdStLoadUpd, 637 []>, RegConstraint<"$addr.offreg = $ea_result">, 638 NoEncode<"$ea_result">; 639 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc:$ea_result), 640 (ins memrr:$addr), 641 "lwzux $rD, $addr", LdStLoadUpd, 642 []>, RegConstraint<"$addr.offreg = $ea_result">, 643 NoEncode<"$ea_result">; 644 } 645 } 646 647 648 // Full 8-byte loads. 649 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 650 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 651 "ld $rD, $src", LdStLD, 652 [(set G8RC:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 653 def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src), 654 "ld $rD, $src", LdStLD, 655 []>, isPPC64; 656 // The following three definitions are selected for small code model only. 657 // Otherwise, we need to create two instructions to form a 32-bit offset, 658 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 659 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 660 "#LDtoc", 661 [(set G8RC:$rD, 662 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 663 def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 664 "#LDtocJTI", 665 [(set G8RC:$rD, 666 (PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64; 667 def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 668 "#LDtocCPT", 669 [(set G8RC:$rD, 670 (PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64; 671 672 let hasSideEffects = 1 in { 673 let RST = 2, DS = 2 in 674 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg), 675 "ld 2, 8($reg)", LdStLD, 676 [(PPCload_toc G8RC:$reg)]>, isPPC64; 677 678 let RST = 2, DS = 10, RA = 1 in 679 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 680 "ld 2, 40(1)", LdStLD, 681 [(PPCtoc_restore)]>, isPPC64; 682 } 683 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 684 "ldx $rD, $src", LdStLD, 685 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 686 let isCodeGenOnly = 1 in 687 def LDXu : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 688 "ldx $rD, $src", LdStLD, 689 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 690 691 let mayLoad = 1 in 692 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 693 "ldu $rD, $addr", LdStLDU, 694 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 695 NoEncode<"$ea_result">; 696 697 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc:$ea_result), 698 (ins memrr:$addr), 699 "ldux $rD, $addr", LdStLDU, 700 []>, RegConstraint<"$addr.offreg = $ea_result">, 701 NoEncode<"$ea_result">, isPPC64; 702 } 703 704 def : Pat<(PPCload ixaddr:$src), 705 (LD ixaddr:$src)>; 706 def : Pat<(PPCload xaddr:$src), 707 (LDX xaddr:$src)>; 708 709 // Support for medium and large code model. 710 def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 711 "#ADDIStocHA", 712 [(set G8RC:$rD, 713 (PPCaddisTocHA G8RC:$reg, tglobaladdr:$disp))]>, 714 isPPC64; 715 def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 716 "#LDtocL", 717 [(set G8RC:$rD, 718 (PPCldTocL tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 719 def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 720 "#ADDItocL", 721 [(set G8RC:$rD, 722 (PPCaddiTocL G8RC:$reg, tglobaladdr:$disp))]>, isPPC64; 723 724 // Support for thread-local storage. 725 def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 726 "#ADDISgotTprelHA", 727 [(set G8RC:$rD, 728 (PPCaddisGotTprelHA G8RC:$reg, 729 tglobaltlsaddr:$disp))]>, 730 isPPC64; 731 def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg), 732 "#LDgotTprelL", 733 [(set G8RC:$rD, 734 (PPCldGotTprelL tglobaltlsaddr:$disp, G8RC:$reg))]>, 735 isPPC64; 736 def : Pat<(PPCaddTls G8RC:$in, tglobaltlsaddr:$g), 737 (ADD8TLS G8RC:$in, tglobaltlsaddr:$g)>; 738 def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 739 "#ADDIStlsgdHA", 740 [(set G8RC:$rD, 741 (PPCaddisTlsgdHA G8RC:$reg, tglobaltlsaddr:$disp))]>, 742 isPPC64; 743 def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 744 "#ADDItlsgdL", 745 [(set G8RC:$rD, 746 (PPCaddiTlsgdL G8RC:$reg, tglobaltlsaddr:$disp))]>, 747 isPPC64; 748 def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym), 749 "#GETtlsADDR", 750 [(set G8RC:$rD, 751 (PPCgetTlsAddr G8RC:$reg, tglobaltlsaddr:$sym))]>, 752 isPPC64; 753 def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 754 "#ADDIStlsldHA", 755 [(set G8RC:$rD, 756 (PPCaddisTlsldHA G8RC:$reg, tglobaltlsaddr:$disp))]>, 757 isPPC64; 758 def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 759 "#ADDItlsldL", 760 [(set G8RC:$rD, 761 (PPCaddiTlsldL G8RC:$reg, tglobaltlsaddr:$disp))]>, 762 isPPC64; 763 def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym), 764 "#GETtlsldADDR", 765 [(set G8RC:$rD, 766 (PPCgetTlsldAddr G8RC:$reg, tglobaltlsaddr:$sym))]>, 767 isPPC64; 768 def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 769 "#ADDISdtprelHA", 770 [(set G8RC:$rD, 771 (PPCaddisDtprelHA G8RC:$reg, 772 tglobaltlsaddr:$disp))]>, 773 isPPC64; 774 def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 775 "#ADDIdtprelL", 776 [(set G8RC:$rD, 777 (PPCaddiDtprelL G8RC:$reg, tglobaltlsaddr:$disp))]>, 778 isPPC64; 779 780 let PPC970_Unit = 2 in { 781 // Truncating stores. 782 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 783 "stb $rS, $src", LdStStore, 784 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 785 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 786 "sth $rS, $src", LdStStore, 787 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 788 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 789 "stw $rS, $src", LdStStore, 790 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 791 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 792 "stbx $rS, $dst", LdStStore, 793 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 794 PPC970_DGroup_Cracked; 795 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 796 "sthx $rS, $dst", LdStStore, 797 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 798 PPC970_DGroup_Cracked; 799 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 800 "stwx $rS, $dst", LdStStore, 801 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 802 PPC970_DGroup_Cracked; 803 // Normal 8-byte stores. 804 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 805 "std $rS, $dst", LdStSTD, 806 [(aligned4store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 807 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 808 "stdx $rS, $dst", LdStSTD, 809 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 810 PPC970_DGroup_Cracked; 811 } 812 813 let PPC970_Unit = 2 in { 814 815 def STBU8 : DForm_1a<39, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 816 symbolLo:$ptroff, ptr_rc:$ptrreg), 817 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd, 818 [(set ptr_rc:$ea_res, 819 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 820 iaddroff:$ptroff))]>, 821 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 822 def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 823 symbolLo:$ptroff, ptr_rc:$ptrreg), 824 "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd, 825 [(set ptr_rc:$ea_res, 826 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 827 iaddroff:$ptroff))]>, 828 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 829 830 def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 831 symbolLo:$ptroff, ptr_rc:$ptrreg), 832 "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd, 833 [(set ptr_rc:$ea_res, 834 (pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, 835 iaddroff:$ptroff))]>, 836 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 837 838 def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 839 s16immX4:$ptroff, ptr_rc:$ptrreg), 840 "stdu $rS, $ptroff($ptrreg)", LdStSTDU, 841 [(set ptr_rc:$ea_res, 842 (aligned4pre_store G8RC:$rS, ptr_rc:$ptrreg, 843 iaddroff:$ptroff))]>, 844 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 845 isPPC64; 846 847 848 def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res), 849 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 850 "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd, 851 [(set ptr_rc:$ea_res, 852 (pre_truncsti8 G8RC:$rS, 853 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 854 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 855 PPC970_DGroup_Cracked; 856 857 def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res), 858 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 859 "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd, 860 [(set ptr_rc:$ea_res, 861 (pre_truncsti16 G8RC:$rS, 862 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 863 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 864 PPC970_DGroup_Cracked; 865 866 def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res), 867 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 868 "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd, 869 [(set ptr_rc:$ea_res, 870 (pre_truncsti32 G8RC:$rS, 871 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 872 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 873 PPC970_DGroup_Cracked; 874 875 def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res), 876 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 877 "stdux $rS, $ptroff, $ptrreg", LdStSTDU, 878 [(set ptr_rc:$ea_res, 879 (pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 880 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 881 PPC970_DGroup_Cracked, isPPC64; 882 883 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 884 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 885 "std $rT, $dst", LdStSTD, 886 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 887 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 888 "stdx $rT, $dst", LdStSTD, 889 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 890 PPC970_DGroup_Cracked; 891 } 892 893 894 895 //===----------------------------------------------------------------------===// 896 // Floating point instructions. 897 // 898 899 900 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 901 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 902 "fcfid $frD, $frB", FPGeneral, 903 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 904 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 905 "fctidz $frD, $frB", FPGeneral, 906 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 907 } 908 909 910 //===----------------------------------------------------------------------===// 911 // Instruction Patterns 912 // 913 914 // Extensions and truncates to/from 32-bit regs. 915 def : Pat<(i64 (zext GPRC:$in)), 916 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32), 917 0, 32)>; 918 def : Pat<(i64 (anyext GPRC:$in)), 919 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>; 920 def : Pat<(i32 (trunc G8RC:$in)), 921 (EXTRACT_SUBREG G8RC:$in, sub_32)>; 922 923 // Extending loads with i64 targets. 924 def : Pat<(zextloadi1 iaddr:$src), 925 (LBZ8 iaddr:$src)>; 926 def : Pat<(zextloadi1 xaddr:$src), 927 (LBZX8 xaddr:$src)>; 928 def : Pat<(extloadi1 iaddr:$src), 929 (LBZ8 iaddr:$src)>; 930 def : Pat<(extloadi1 xaddr:$src), 931 (LBZX8 xaddr:$src)>; 932 def : Pat<(extloadi8 iaddr:$src), 933 (LBZ8 iaddr:$src)>; 934 def : Pat<(extloadi8 xaddr:$src), 935 (LBZX8 xaddr:$src)>; 936 def : Pat<(extloadi16 iaddr:$src), 937 (LHZ8 iaddr:$src)>; 938 def : Pat<(extloadi16 xaddr:$src), 939 (LHZX8 xaddr:$src)>; 940 def : Pat<(extloadi32 iaddr:$src), 941 (LWZ8 iaddr:$src)>; 942 def : Pat<(extloadi32 xaddr:$src), 943 (LWZX8 xaddr:$src)>; 944 945 // Standard shifts. These are represented separately from the real shifts above 946 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift 947 // amounts. 948 def : Pat<(sra G8RC:$rS, GPRC:$rB), 949 (SRAD G8RC:$rS, GPRC:$rB)>; 950 def : Pat<(srl G8RC:$rS, GPRC:$rB), 951 (SRD G8RC:$rS, GPRC:$rB)>; 952 def : Pat<(shl G8RC:$rS, GPRC:$rB), 953 (SLD G8RC:$rS, GPRC:$rB)>; 954 955 // SHL/SRL 956 def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 957 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 958 def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 959 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 960 961 // ROTL 962 def : Pat<(rotl G8RC:$in, GPRC:$sh), 963 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 964 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 965 (RLDICL G8RC:$in, imm:$imm, 0)>; 966 967 // Hi and Lo for Darwin Global Addresses. 968 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 969 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 970 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 971 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 972 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 973 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 974 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 975 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 976 def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in), 977 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>; 978 def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in), 979 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>; 980 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 981 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 982 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 983 (ADDIS8 G8RC:$in, tconstpool:$g)>; 984 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 985 (ADDIS8 G8RC:$in, tjumptable:$g)>; 986 def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 987 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 988 989 // Patterns to match r+r indexed loads and stores for 990 // addresses without at least 4-byte alignment. 991 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 992 (LWAX xoaddr:$src)>; 993 def : Pat<(i64 (unaligned4load xoaddr:$src)), 994 (LDX xoaddr:$src)>; 995 def : Pat<(unaligned4store G8RC:$rS, xoaddr:$dst), 996 (STDX G8RC:$rS, xoaddr:$dst)>; 997 998
