1 //===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the sign and zero extension operations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 let neverHasSideEffects = 1 in { 15 let Defs = [AX], Uses = [AL] in 16 def CBW : I<0x98, RawFrm, (outs), (ins), 17 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL) 18 let Defs = [EAX], Uses = [AX] in 19 def CWDE : I<0x98, RawFrm, (outs), (ins), 20 "{cwtl|cwde}", []>; // EAX = signext(AX) 21 22 let Defs = [AX,DX], Uses = [AX] in 23 def CWD : I<0x99, RawFrm, (outs), (ins), 24 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX) 25 let Defs = [EAX,EDX], Uses = [EAX] in 26 def CDQ : I<0x99, RawFrm, (outs), (ins), 27 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX) 28 29 30 let Defs = [RAX], Uses = [EAX] in 31 def CDQE : RI<0x98, RawFrm, (outs), (ins), 32 "{cltq|cdqe}", []>; // RAX = signext(EAX) 33 34 let Defs = [RAX,RDX], Uses = [RAX] in 35 def CQO : RI<0x99, RawFrm, (outs), (ins), 36 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX) 37 } 38 39 40 41 // Sign/Zero extenders 42 let neverHasSideEffects = 1 in { 43 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), 44 "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>, 45 TB, OpSize; 46 let mayLoad = 1 in 47 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), 48 "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_M8>, 49 TB, OpSize; 50 } // neverHasSideEffects = 1 51 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src), 52 "movs{bl|x}\t{$src, $dst|$dst, $src}", 53 [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB; 54 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), 55 "movs{bl|x}\t{$src, $dst|$dst, $src}", 56 [(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB; 57 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), 58 "movs{wl|x}\t{$src, $dst|$dst, $src}", 59 [(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB; 60 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 61 "movs{wl|x}\t{$src, $dst|$dst, $src}", 62 [(set GR32:$dst, (sextloadi32i16 addr:$src))], IIC_MOVSX>, 63 TB; 64 65 let neverHasSideEffects = 1 in { 66 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), 67 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_R8>, 68 TB, OpSize; 69 let mayLoad = 1 in 70 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), 71 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_M8>, 72 TB, OpSize; 73 } // neverHasSideEffects = 1 74 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), 75 "movz{bl|x}\t{$src, $dst|$dst, $src}", 76 [(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB; 77 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), 78 "movz{bl|x}\t{$src, $dst|$dst, $src}", 79 [(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB; 80 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), 81 "movz{wl|x}\t{$src, $dst|$dst, $src}", 82 [(set GR32:$dst, (zext GR16:$src))], IIC_MOVZX>, TB; 83 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 84 "movz{wl|x}\t{$src, $dst|$dst, $src}", 85 [(set GR32:$dst, (zextloadi32i16 addr:$src))], IIC_MOVZX>, 86 TB; 87 88 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8 89 // except that they use GR32_NOREX for the output operand register class 90 // instead of GR32. This allows them to operate on h registers on x86-64. 91 let neverHasSideEffects = 1, isCodeGenOnly = 1 in { 92 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg, 93 (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), 94 "movz{bl|x}\t{$src, $dst|$dst, $src}", 95 [], IIC_MOVZX>, TB; 96 let mayLoad = 1 in 97 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem, 98 (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), 99 "movz{bl|x}\t{$src, $dst|$dst, $src}", 100 [], IIC_MOVZX>, TB; 101 } 102 103 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register 104 // operand, which makes it a rare instruction with an 8-bit register 105 // operand that can never access an h register. If support for h registers 106 // were generalized, this would require a special register class. 107 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), 108 "movs{bq|x}\t{$src, $dst|$dst, $src}", 109 [(set GR64:$dst, (sext GR8:$src))], IIC_MOVSX>, TB; 110 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), 111 "movs{bq|x}\t{$src, $dst|$dst, $src}", 112 [(set GR64:$dst, (sextloadi64i8 addr:$src))], IIC_MOVSX>, 113 TB; 114 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), 115 "movs{wq|x}\t{$src, $dst|$dst, $src}", 116 [(set GR64:$dst, (sext GR16:$src))], IIC_MOVSX>, TB; 117 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 118 "movs{wq|x}\t{$src, $dst|$dst, $src}", 119 [(set GR64:$dst, (sextloadi64i16 addr:$src))], IIC_MOVSX>, 120 TB; 121 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 122 "movs{lq|xd}\t{$src, $dst|$dst, $src}", 123 [(set GR64:$dst, (sext GR32:$src))], IIC_MOVSX>; 124 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), 125 "movs{lq|xd}\t{$src, $dst|$dst, $src}", 126 [(set GR64:$dst, (sextloadi64i32 addr:$src))], IIC_MOVSX>; 127 128 // movzbq and movzwq encodings for the disassembler 129 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src), 130 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, 131 TB; 132 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src), 133 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, 134 TB; 135 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), 136 "movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, 137 TB; 138 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 139 "movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, 140 TB; 141 142 // FIXME: These should be Pat patterns. 143 let isCodeGenOnly = 1 in { 144 145 // Use movzbl instead of movzbq when the destination is a register; it's 146 // equivalent due to implicit zero-extending, and it has a smaller encoding. 147 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), 148 "", [(set GR64:$dst, (zext GR8:$src))], IIC_MOVZX>, TB; 149 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), 150 "", [(set GR64:$dst, (zextloadi64i8 addr:$src))], IIC_MOVZX>, 151 TB; 152 // Use movzwl instead of movzwq when the destination is a register; it's 153 // equivalent due to implicit zero-extending, and it has a smaller encoding. 154 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), 155 "", [(set GR64:$dst, (zext GR16:$src))], IIC_MOVZX>, TB; 156 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 157 "", [(set GR64:$dst, (zextloadi64i16 addr:$src))], 158 IIC_MOVZX>, TB; 159 160 // There's no movzlq instruction, but movl can be used for this purpose, using 161 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero 162 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit 163 // zero-extension, however this isn't possible when the 32-bit value is 164 // defined by a truncate or is copied from something where the high bits aren't 165 // necessarily all zero. In such cases, we fall back to these explicit zext 166 // instructions. 167 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src), 168 "", [(set GR64:$dst, (zext GR32:$src))], IIC_MOVZX>; 169 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), 170 "", [(set GR64:$dst, (zextloadi64i32 addr:$src))], 171 IIC_MOVZX>; 172 } 173 174
