1 //===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 MMX instruction set, defining the instructions, 11 // and properties of the instructions which are needed for code generation, 12 // machine code emission, and analysis. 13 // 14 // All instructions that use MMX should be in this file, even if they also use 15 // SSE. 16 // 17 //===----------------------------------------------------------------------===// 18 19 //===----------------------------------------------------------------------===// 20 // MMX Multiclasses 21 //===----------------------------------------------------------------------===// 22 23 def MMX_INTALU_ITINS : OpndItins< 24 IIC_MMX_ALU_RR, IIC_MMX_ALU_RM 25 >; 26 27 def MMX_INTALUQ_ITINS : OpndItins< 28 IIC_MMX_ALUQ_RR, IIC_MMX_ALUQ_RM 29 >; 30 31 def MMX_PHADDSUBW : OpndItins< 32 IIC_MMX_PHADDSUBW_RR, IIC_MMX_PHADDSUBW_RM 33 >; 34 35 def MMX_PHADDSUBD : OpndItins< 36 IIC_MMX_PHADDSUBD_RR, IIC_MMX_PHADDSUBD_RM 37 >; 38 39 def MMX_PMUL_ITINS : OpndItins< 40 IIC_MMX_PMUL, IIC_MMX_PMUL 41 >; 42 43 def MMX_PSADBW_ITINS : OpndItins< 44 IIC_MMX_PSADBW, IIC_MMX_PSADBW 45 >; 46 47 def MMX_MISC_FUNC_ITINS : OpndItins< 48 IIC_MMX_MISC_FUNC_MEM, IIC_MMX_MISC_FUNC_REG 49 >; 50 51 def MMX_SHIFT_ITINS : ShiftOpndItins< 52 IIC_MMX_SHIFT_RR, IIC_MMX_SHIFT_RM, IIC_MMX_SHIFT_RI 53 >; 54 55 def MMX_UNPCK_H_ITINS : OpndItins< 56 IIC_MMX_UNPCK_H_RR, IIC_MMX_UNPCK_H_RM 57 >; 58 59 def MMX_UNPCK_L_ITINS : OpndItins< 60 IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L 61 >; 62 63 def MMX_PCK_ITINS : OpndItins< 64 IIC_MMX_PCK_RR, IIC_MMX_PCK_RM 65 >; 66 67 def MMX_PSHUF_ITINS : OpndItins< 68 IIC_MMX_PSHUF, IIC_MMX_PSHUF 69 >; 70 71 def MMX_CVT_PD_ITINS : OpndItins< 72 IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM 73 >; 74 75 def MMX_CVT_PS_ITINS : OpndItins< 76 IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM 77 >; 78 79 let Constraints = "$src1 = $dst" in { 80 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic. 81 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp. 82 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, 83 OpndItins itins, bit Commutable = 0> { 84 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 85 (ins VR64:$src1, VR64:$src2), 86 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 87 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr> { 88 let isCommutable = Commutable; 89 } 90 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 91 (ins VR64:$src1, i64mem:$src2), 92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 93 [(set VR64:$dst, (IntId VR64:$src1, 94 (bitconvert (load_mmx addr:$src2))))], 95 itins.rm>; 96 } 97 98 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, 99 string OpcodeStr, Intrinsic IntId, 100 Intrinsic IntId2, ShiftOpndItins itins> { 101 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 102 (ins VR64:$src1, VR64:$src2), 103 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 104 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>; 105 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 106 (ins VR64:$src1, i64mem:$src2), 107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 108 [(set VR64:$dst, (IntId VR64:$src1, 109 (bitconvert (load_mmx addr:$src2))))], 110 itins.rm>; 111 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), 112 (ins VR64:$src1, i32i8imm:$src2), 113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 114 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))], itins.ri>; 115 } 116 } 117 118 /// Unary MMX instructions requiring SSSE3. 119 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr, 120 Intrinsic IntId64, OpndItins itins> { 121 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), 122 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 123 [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>; 124 125 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), 126 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 127 [(set VR64:$dst, 128 (IntId64 (bitconvert (memopmmx addr:$src))))], 129 itins.rm>; 130 } 131 132 /// Binary MMX instructions requiring SSSE3. 133 let ImmT = NoImm, Constraints = "$src1 = $dst" in { 134 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr, 135 Intrinsic IntId64, OpndItins itins> { 136 let isCommutable = 0 in 137 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), 138 (ins VR64:$src1, VR64:$src2), 139 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 140 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))], itins.rr>; 141 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), 142 (ins VR64:$src1, i64mem:$src2), 143 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 144 [(set VR64:$dst, 145 (IntId64 VR64:$src1, 146 (bitconvert (memopmmx addr:$src2))))], itins.rm>; 147 } 148 } 149 150 /// PALIGN MMX instructions (require SSSE3). 151 multiclass ssse3_palign_mm<string asm, Intrinsic IntId> { 152 def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), 153 (ins VR64:$src1, VR64:$src2, i8imm:$src3), 154 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 155 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>; 156 def R64irm : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), 157 (ins VR64:$src1, i64mem:$src2, i8imm:$src3), 158 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 159 [(set VR64:$dst, (IntId VR64:$src1, 160 (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>; 161 } 162 163 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 164 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, 165 string asm, OpndItins itins, Domain d> { 166 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, 167 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>; 168 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, 169 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>; 170 } 171 172 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, 173 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, 174 PatFrag ld_frag, string asm, Domain d> { 175 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2), 176 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], 177 IIC_DEFAULT, d>; 178 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst), 179 (ins DstRC:$src1, x86memop:$src2), asm, 180 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], 181 IIC_DEFAULT, d>; 182 } 183 184 //===----------------------------------------------------------------------===// 185 // MMX EMMS Instruction 186 //===----------------------------------------------------------------------===// 187 188 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", 189 [(int_x86_mmx_emms)]>; 190 191 //===----------------------------------------------------------------------===// 192 // MMX Scalar Instructions 193 //===----------------------------------------------------------------------===// 194 195 // Data Transfer Instructions 196 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), 197 "movd\t{$src, $dst|$dst, $src}", 198 [(set VR64:$dst, 199 (x86mmx (scalar_to_vector GR32:$src)))], 200 IIC_MMX_MOV_MM_RM>; 201 let canFoldAsLoad = 1 in 202 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), 203 "movd\t{$src, $dst|$dst, $src}", 204 [(set VR64:$dst, 205 (x86mmx (scalar_to_vector (loadi32 addr:$src))))], 206 IIC_MMX_MOV_MM_RM>; 207 let mayStore = 1 in 208 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), 209 "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_MM_RM>; 210 211 // Low word of MMX to GPR. 212 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1, 213 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>; 214 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src), 215 "movd\t{$src, $dst|$dst, $src}", 216 [(set GR32:$dst, 217 (MMX_X86movd2w (x86mmx VR64:$src)))], IIC_MMX_MOV_REG_MM>; 218 219 let neverHasSideEffects = 1 in 220 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), 221 "movd\t{$src, $dst|$dst, $src}", 222 [], IIC_MMX_MOV_MM_RM>; 223 224 // These are 64 bit moves, but since the OS X assembler doesn't 225 // recognize a register-register movq, we write them as 226 // movd. 227 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg, 228 (outs GR64:$dst), (ins VR64:$src), 229 "movd\t{$src, $dst|$dst, $src}", 230 [(set GR64:$dst, 231 (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>; 232 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), 233 "movd\t{$src, $dst|$dst, $src}", 234 [(set VR64:$dst, 235 (bitconvert GR64:$src))], IIC_MMX_MOV_MM_RM>; 236 let neverHasSideEffects = 1 in 237 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), 238 "movq\t{$src, $dst|$dst, $src}", [], 239 IIC_MMX_MOVQ_RR>; 240 let canFoldAsLoad = 1 in 241 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), 242 "movq\t{$src, $dst|$dst, $src}", 243 [(set VR64:$dst, (load_mmx addr:$src))], 244 IIC_MMX_MOVQ_RM>; 245 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), 246 "movq\t{$src, $dst|$dst, $src}", 247 [(store (x86mmx VR64:$src), addr:$dst)], 248 IIC_MMX_MOVQ_RM>; 249 250 def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), 251 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}", 252 [(set VR64:$dst, 253 (x86mmx (bitconvert 254 (i64 (vector_extract (v2i64 VR128:$src), 255 (iPTR 0))))))], 256 IIC_MMX_MOVQ_RR>; 257 258 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst), 259 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", 260 [(set VR128:$dst, 261 (v2i64 262 (scalar_to_vector 263 (i64 (bitconvert (x86mmx VR64:$src))))))], 264 IIC_MMX_MOVQ_RR>; 265 266 let neverHasSideEffects = 1 in 267 def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst), 268 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", 269 [], IIC_MMX_MOVQ_RR>; 270 271 def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), 272 (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}", 273 [], IIC_MMX_MOVQ_RR>; 274 275 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), 276 "movntq\t{$src, $dst|$dst, $src}", 277 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)], 278 IIC_MMX_MOVQ_RM>; 279 280 let AddedComplexity = 15 in 281 // movd to MMX register zero-extends 282 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), 283 "movd\t{$src, $dst|$dst, $src}", 284 [(set VR64:$dst, 285 (x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))))], 286 IIC_MMX_MOV_MM_RM>; 287 let AddedComplexity = 20 in 288 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), 289 (ins i32mem:$src), 290 "movd\t{$src, $dst|$dst, $src}", 291 [(set VR64:$dst, 292 (x86mmx (X86vzmovl (x86mmx 293 (scalar_to_vector (loadi32 addr:$src))))))], 294 IIC_MMX_MOV_MM_RM>; 295 296 // Arithmetic Instructions 297 defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b, 298 MMX_INTALU_ITINS>; 299 defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w, 300 MMX_INTALU_ITINS>; 301 defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d, 302 MMX_INTALU_ITINS>; 303 // -- Addition 304 defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 305 MMX_INTALU_ITINS, 1>; 306 defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 307 MMX_INTALU_ITINS, 1>; 308 defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 309 MMX_INTALU_ITINS, 1>; 310 defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 311 MMX_INTALUQ_ITINS, 1>; 312 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 313 MMX_INTALU_ITINS, 1>; 314 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 315 MMX_INTALU_ITINS, 1>; 316 317 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 318 MMX_INTALU_ITINS, 1>; 319 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 320 MMX_INTALU_ITINS, 1>; 321 322 defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w, 323 MMX_PHADDSUBW>; 324 defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d, 325 MMX_PHADDSUBD>; 326 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw, 327 MMX_PHADDSUBW>; 328 329 330 // -- Subtraction 331 defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b, 332 MMX_INTALU_ITINS>; 333 defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w, 334 MMX_INTALU_ITINS, 1>; 335 defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d, 336 MMX_INTALU_ITINS, 1>; 337 defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q, 338 MMX_INTALUQ_ITINS, 1>; 339 340 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b, 341 MMX_INTALU_ITINS, 1>; 342 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w, 343 MMX_INTALU_ITINS, 1>; 344 345 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b, 346 MMX_INTALU_ITINS, 1>; 347 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w, 348 MMX_INTALU_ITINS, 1>; 349 350 defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w, 351 MMX_PHADDSUBW>; 352 defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d, 353 MMX_PHADDSUBD>; 354 defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw, 355 MMX_PHADDSUBW>; 356 357 // -- Multiplication 358 defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 359 MMX_PMUL_ITINS, 1>; 360 361 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 362 MMX_PMUL_ITINS, 1>; 363 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 364 MMX_PMUL_ITINS, 1>; 365 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 366 MMX_PMUL_ITINS, 1>; 367 let isCommutable = 1 in 368 defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", 369 int_x86_ssse3_pmul_hr_sw, MMX_PMUL_ITINS>; 370 371 // -- Miscellanea 372 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 373 MMX_PMUL_ITINS, 1>; 374 375 defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", 376 int_x86_ssse3_pmadd_ub_sw, MMX_PMUL_ITINS>; 377 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 378 MMX_MISC_FUNC_ITINS, 1>; 379 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 380 MMX_MISC_FUNC_ITINS, 1>; 381 382 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 383 MMX_MISC_FUNC_ITINS, 1>; 384 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 385 MMX_MISC_FUNC_ITINS, 1>; 386 387 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 388 MMX_MISC_FUNC_ITINS, 1>; 389 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 390 MMX_MISC_FUNC_ITINS, 1>; 391 392 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 393 MMX_PSADBW_ITINS, 1>; 394 395 defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b, 396 MMX_MISC_FUNC_ITINS>; 397 defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w, 398 MMX_MISC_FUNC_ITINS>; 399 defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d, 400 MMX_MISC_FUNC_ITINS>; 401 let Constraints = "$src1 = $dst" in 402 defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>; 403 404 // Logical Instructions 405 defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 406 MMX_INTALU_ITINS, 1>; 407 defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 408 MMX_INTALU_ITINS, 1>; 409 defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 410 MMX_INTALU_ITINS, 1>; 411 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, 412 MMX_INTALU_ITINS>; 413 414 // Shift Instructions 415 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", 416 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w, 417 MMX_SHIFT_ITINS>; 418 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", 419 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d, 420 MMX_SHIFT_ITINS>; 421 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", 422 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q, 423 MMX_SHIFT_ITINS>; 424 425 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", 426 int_x86_mmx_psll_w, int_x86_mmx_pslli_w, 427 MMX_SHIFT_ITINS>; 428 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", 429 int_x86_mmx_psll_d, int_x86_mmx_pslli_d, 430 MMX_SHIFT_ITINS>; 431 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", 432 int_x86_mmx_psll_q, int_x86_mmx_pslli_q, 433 MMX_SHIFT_ITINS>; 434 435 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", 436 int_x86_mmx_psra_w, int_x86_mmx_psrai_w, 437 MMX_SHIFT_ITINS>; 438 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", 439 int_x86_mmx_psra_d, int_x86_mmx_psrai_d, 440 MMX_SHIFT_ITINS>; 441 442 // Comparison Instructions 443 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b, 444 MMX_INTALU_ITINS>; 445 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w, 446 MMX_INTALU_ITINS>; 447 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d, 448 MMX_INTALU_ITINS>; 449 450 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b, 451 MMX_INTALU_ITINS>; 452 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w, 453 MMX_INTALU_ITINS>; 454 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d, 455 MMX_INTALU_ITINS>; 456 457 // -- Unpack Instructions 458 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw", 459 int_x86_mmx_punpckhbw, 460 MMX_UNPCK_H_ITINS>; 461 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd", 462 int_x86_mmx_punpckhwd, 463 MMX_UNPCK_H_ITINS>; 464 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq", 465 int_x86_mmx_punpckhdq, 466 MMX_UNPCK_H_ITINS>; 467 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw", 468 int_x86_mmx_punpcklbw, 469 MMX_UNPCK_L_ITINS>; 470 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd", 471 int_x86_mmx_punpcklwd, 472 MMX_UNPCK_L_ITINS>; 473 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq", 474 int_x86_mmx_punpckldq, 475 MMX_UNPCK_L_ITINS>; 476 477 // -- Pack Instructions 478 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb, 479 MMX_PCK_ITINS>; 480 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw, 481 MMX_PCK_ITINS>; 482 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb, 483 MMX_PCK_ITINS>; 484 485 // -- Shuffle Instructions 486 defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b, 487 MMX_PSHUF_ITINS>; 488 489 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg, 490 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2), 491 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 492 [(set VR64:$dst, 493 (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))], 494 IIC_MMX_PSHUF>; 495 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem, 496 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2), 497 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 498 [(set VR64:$dst, 499 (int_x86_sse_pshuf_w (load_mmx addr:$src1), 500 imm:$src2))], 501 IIC_MMX_PSHUF>; 502 503 504 505 506 // -- Conversion Instructions 507 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi, 508 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}", 509 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB; 510 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi, 511 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}", 512 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize; 513 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi, 514 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}", 515 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB; 516 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi, 517 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}", 518 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize; 519 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd, 520 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}", 521 MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize; 522 let Constraints = "$src1 = $dst" in { 523 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128, 524 int_x86_sse_cvtpi2ps, 525 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}", 526 SSEPackedSingle>, TB; 527 } 528 529 // Extract / Insert 530 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg, 531 (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2), 532 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 533 [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1, 534 (iPTR imm:$src2)))], 535 IIC_MMX_PEXTR>; 536 let Constraints = "$src1 = $dst" in { 537 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg, 538 (outs VR64:$dst), 539 (ins VR64:$src1, GR32:$src2, i32i8imm:$src3), 540 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", 541 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, 542 GR32:$src2, (iPTR imm:$src3)))], 543 IIC_MMX_PINSRW>; 544 545 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem, 546 (outs VR64:$dst), 547 (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3), 548 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", 549 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, 550 (i32 (anyext (loadi16 addr:$src2))), 551 (iPTR imm:$src3)))], 552 IIC_MMX_PINSRW>; 553 } 554 555 // Mask creation 556 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src), 557 "pmovmskb\t{$src, $dst|$dst, $src}", 558 [(set GR32:$dst, 559 (int_x86_mmx_pmovmskb VR64:$src))]>; 560 561 562 // Low word of XMM to MMX. 563 def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1, 564 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>; 565 566 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)), 567 (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>; 568 569 def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))), 570 (x86mmx (MMX_MOVQ64rm addr:$src))>; 571 572 // Misc. 573 let Uses = [EDI] in 574 def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), 575 "maskmovq\t{$mask, $src|$src, $mask}", 576 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)], 577 IIC_MMX_MASKMOV>; 578 let Uses = [RDI] in 579 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), 580 "maskmovq\t{$mask, $src|$src, $mask}", 581 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)], 582 IIC_MMX_MASKMOV>; 583 584 // 64-bit bit convert. 585 let Predicates = [HasSSE2] in { 586 def : Pat<(x86mmx (bitconvert (i64 GR64:$src))), 587 (MMX_MOVD64to64rr GR64:$src)>; 588 def : Pat<(i64 (bitconvert (x86mmx VR64:$src))), 589 (MMX_MOVD64from64rr VR64:$src)>; 590 def : Pat<(f64 (bitconvert (x86mmx VR64:$src))), 591 (MMX_MOVQ2FR64rr VR64:$src)>; 592 def : Pat<(x86mmx (bitconvert (f64 FR64:$src))), 593 (MMX_MOVFR642Qrr FR64:$src)>; 594 } 595 596 597
