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      1 ; RUN: llc < %s -verify-machineinstrs
      2 ; RUN: llc < %s -verify-machineinstrs -O0
      3 ; PR12177
      4 ;
      5 ; This test case spills a QQQQ register.
      6 ;
      7 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
      8 target triple = "armv7-none-linux-gnueabi"
      9 
     10 %0 = type { %1*, i32, i32, i32, i8 }
     11 %1 = type { i32 (...)** }
     12 %2 = type { i8*, i8*, i8*, i32 }
     13 %3 = type { %4 }
     14 %4 = type { i32 (...)**, %2, %4*, i8, i8 }
     15 
     16 declare arm_aapcs_vfpcc void @func1(%0*, float* nocapture, float* nocapture, %2*) nounwind
     17 
     18 declare arm_aapcs_vfpcc %0** @func2()
     19 
     20 declare arm_aapcs_vfpcc %2* @func3(%2*, %2*, i32)
     21 
     22 declare arm_aapcs_vfpcc %2** @func4()
     23 
     24 define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 {
     25   call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
     26   %2 = call arm_aapcs_vfpcc  %0** @func2() nounwind
     27   %3 = load %0** %2, align 4, !tbaa !0
     28   store float 0.000000e+00, float* undef, align 4
     29   %4 = call arm_aapcs_vfpcc  %2* @func3(%2* undef, %2* undef, i32 2956) nounwind
     30   call arm_aapcs_vfpcc  void @func1(%0* %3, float* undef, float* undef, %2* undef)
     31   %5 = call arm_aapcs_vfpcc  %0** @func2() nounwind
     32   store float 1.000000e+00, float* undef, align 4
     33   call arm_aapcs_vfpcc  void @func1(%0* undef, float* undef, float* undef, %2* undef)
     34   store float 1.500000e+01, float* undef, align 4
     35   %6 = call arm_aapcs_vfpcc  %2** @func4() nounwind
     36   %7 = call arm_aapcs_vfpcc  %2* @func3(%2* undef, %2* undef, i32 2971) nounwind
     37   %8 = fadd float undef, -1.000000e+05
     38   store float %8, float* undef, align 16, !tbaa !3
     39   %9 = call arm_aapcs_vfpcc  i32 @rand() nounwind
     40   %10 = fmul float undef, 2.000000e+05
     41   %11 = fadd float %10, -1.000000e+05
     42   store float %11, float* undef, align 4, !tbaa !3
     43   call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
     44   ret void
     45 }
     46 
     47 declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
     48 
     49 declare arm_aapcs_vfpcc i32 @rand()
     50 
     51 !0 = metadata !{metadata !"any pointer", metadata !1}
     52 !1 = metadata !{metadata !"omnipotent char", metadata !2}
     53 !2 = metadata !{metadata !"Simple C/C++ TBAA", null}
     54 !3 = metadata !{metadata !"float", metadata !1}
     55