1 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s 2 ; Check that we generate load instructions with absolute addressing mode. 3 4 @a = external global i32 5 @b = external global i8 6 @c = external global i16 7 @d = external global i64 8 9 define zeroext i8 @absStoreByte() nounwind { 10 ; CHECK: memb(##b){{ *}}={{ *}}r{{[0-9]+}} 11 entry: 12 %0 = load i8* @b, align 1 13 %conv = zext i8 %0 to i32 14 %mul = mul nsw i32 100, %conv 15 %conv1 = trunc i32 %mul to i8 16 store i8 %conv1, i8* @b, align 1 17 ret i8 %conv1 18 } 19 20 define signext i16 @absStoreHalf() nounwind { 21 ; CHECK: memh(##c){{ *}}={{ *}}r{{[0-9]+}} 22 entry: 23 %0 = load i16* @c, align 2 24 %conv = sext i16 %0 to i32 25 %mul = mul nsw i32 100, %conv 26 %conv1 = trunc i32 %mul to i16 27 store i16 %conv1, i16* @c, align 2 28 ret i16 %conv1 29 } 30 31 define i32 @absStoreWord() nounwind { 32 ; CHECK: memw(##a){{ *}}={{ *}}r{{[0-9]+}} 33 entry: 34 %0 = load i32* @a, align 4 35 %mul = mul nsw i32 100, %0 36 store i32 %mul, i32* @a, align 4 37 ret i32 %mul 38 } 39 40 define void @absStoreDouble() nounwind { 41 ; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}} 42 entry: 43 store i64 100, i64* @d, align 8 44 ret void 45 } 46 47
