1 ; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s 2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s 3 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s 4 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s 5 6 ;; These tests should run for all targets 7 8 ;;===-- Basic instruction selection tests ---------------------------------===;; 9 10 11 ;;; i64 12 13 define i64 @icmp_eq_i64(i64 %a, i64 %b) { 14 ; CHECK: setp.eq.s64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 15 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 16 ; CHECK: ret 17 %cmp = icmp eq i64 %a, %b 18 %ret = zext i1 %cmp to i64 19 ret i64 %ret 20 } 21 22 define i64 @icmp_ne_i64(i64 %a, i64 %b) { 23 ; CHECK: setp.ne.s64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 24 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 25 ; CHECK: ret 26 %cmp = icmp ne i64 %a, %b 27 %ret = zext i1 %cmp to i64 28 ret i64 %ret 29 } 30 31 define i64 @icmp_ugt_i64(i64 %a, i64 %b) { 32 ; CHECK: setp.gt.u64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 33 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 34 ; CHECK: ret 35 %cmp = icmp ugt i64 %a, %b 36 %ret = zext i1 %cmp to i64 37 ret i64 %ret 38 } 39 40 define i64 @icmp_uge_i64(i64 %a, i64 %b) { 41 ; CHECK: setp.ge.u64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 42 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 43 ; CHECK: ret 44 %cmp = icmp uge i64 %a, %b 45 %ret = zext i1 %cmp to i64 46 ret i64 %ret 47 } 48 49 define i64 @icmp_ult_i64(i64 %a, i64 %b) { 50 ; CHECK: setp.lt.u64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 51 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 52 ; CHECK: ret 53 %cmp = icmp ult i64 %a, %b 54 %ret = zext i1 %cmp to i64 55 ret i64 %ret 56 } 57 58 define i64 @icmp_ule_i64(i64 %a, i64 %b) { 59 ; CHECK: setp.le.u64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 60 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 61 ; CHECK: ret 62 %cmp = icmp ule i64 %a, %b 63 %ret = zext i1 %cmp to i64 64 ret i64 %ret 65 } 66 67 define i64 @icmp_sgt_i64(i64 %a, i64 %b) { 68 ; CHECK: setp.gt.s64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 69 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 70 ; CHECK: ret 71 %cmp = icmp sgt i64 %a, %b 72 %ret = zext i1 %cmp to i64 73 ret i64 %ret 74 } 75 76 define i64 @icmp_sge_i64(i64 %a, i64 %b) { 77 ; CHECK: setp.ge.s64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 78 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 79 ; CHECK: ret 80 %cmp = icmp sge i64 %a, %b 81 %ret = zext i1 %cmp to i64 82 ret i64 %ret 83 } 84 85 define i64 @icmp_slt_i64(i64 %a, i64 %b) { 86 ; CHECK: setp.lt.s64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 87 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 88 ; CHECK: ret 89 %cmp = icmp slt i64 %a, %b 90 %ret = zext i1 %cmp to i64 91 ret i64 %ret 92 } 93 94 define i64 @icmp_sle_i64(i64 %a, i64 %b) { 95 ; CHECK: setp.le.s64 %p[[P0:[0-9]+]], %rl{{[0-9]+}}, %rl{{[0-9]+}} 96 ; CHECK: selp.u64 %rl{{[0-9]+}}, 1, 0, %p[[P0]] 97 ; CHECK: ret 98 %cmp = icmp sle i64 %a, %b 99 %ret = zext i1 %cmp to i64 100 ret i64 %ret 101 } 102 103 ;;; i32 104 105 define i32 @icmp_eq_i32(i32 %a, i32 %b) { 106 ; CHECK: setp.eq.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 107 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 108 ; CHECK: ret 109 %cmp = icmp eq i32 %a, %b 110 %ret = zext i1 %cmp to i32 111 ret i32 %ret 112 } 113 114 define i32 @icmp_ne_i32(i32 %a, i32 %b) { 115 ; CHECK: setp.ne.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 116 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 117 ; CHECK: ret 118 %cmp = icmp ne i32 %a, %b 119 %ret = zext i1 %cmp to i32 120 ret i32 %ret 121 } 122 123 define i32 @icmp_ugt_i32(i32 %a, i32 %b) { 124 ; CHECK: setp.gt.u32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 125 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 126 ; CHECK: ret 127 %cmp = icmp ugt i32 %a, %b 128 %ret = zext i1 %cmp to i32 129 ret i32 %ret 130 } 131 132 define i32 @icmp_uge_i32(i32 %a, i32 %b) { 133 ; CHECK: setp.ge.u32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 134 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 135 ; CHECK: ret 136 %cmp = icmp uge i32 %a, %b 137 %ret = zext i1 %cmp to i32 138 ret i32 %ret 139 } 140 141 define i32 @icmp_ult_i32(i32 %a, i32 %b) { 142 ; CHECK: setp.lt.u32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 143 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 144 ; CHECK: ret 145 %cmp = icmp ult i32 %a, %b 146 %ret = zext i1 %cmp to i32 147 ret i32 %ret 148 } 149 150 define i32 @icmp_ule_i32(i32 %a, i32 %b) { 151 ; CHECK: setp.le.u32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 152 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 153 ; CHECK: ret 154 %cmp = icmp ule i32 %a, %b 155 %ret = zext i1 %cmp to i32 156 ret i32 %ret 157 } 158 159 define i32 @icmp_sgt_i32(i32 %a, i32 %b) { 160 ; CHECK: setp.gt.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 161 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 162 ; CHECK: ret 163 %cmp = icmp sgt i32 %a, %b 164 %ret = zext i1 %cmp to i32 165 ret i32 %ret 166 } 167 168 define i32 @icmp_sge_i32(i32 %a, i32 %b) { 169 ; CHECK: setp.ge.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 170 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 171 ; CHECK: ret 172 %cmp = icmp sge i32 %a, %b 173 %ret = zext i1 %cmp to i32 174 ret i32 %ret 175 } 176 177 define i32 @icmp_slt_i32(i32 %a, i32 %b) { 178 ; CHECK: setp.lt.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 179 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 180 ; CHECK: ret 181 %cmp = icmp slt i32 %a, %b 182 %ret = zext i1 %cmp to i32 183 ret i32 %ret 184 } 185 186 define i32 @icmp_sle_i32(i32 %a, i32 %b) { 187 ; CHECK: setp.le.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 188 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 189 ; CHECK: ret 190 %cmp = icmp sle i32 %a, %b 191 %ret = zext i1 %cmp to i32 192 ret i32 %ret 193 } 194 195 196 ;;; i16 197 198 define i16 @icmp_eq_i16(i16 %a, i16 %b) { 199 ; CHECK: setp.eq.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 200 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 201 ; CHECK: ret 202 %cmp = icmp eq i16 %a, %b 203 %ret = zext i1 %cmp to i16 204 ret i16 %ret 205 } 206 207 define i16 @icmp_ne_i16(i16 %a, i16 %b) { 208 ; CHECK: setp.ne.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 209 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 210 ; CHECK: ret 211 %cmp = icmp ne i16 %a, %b 212 %ret = zext i1 %cmp to i16 213 ret i16 %ret 214 } 215 216 define i16 @icmp_ugt_i16(i16 %a, i16 %b) { 217 ; CHECK: setp.gt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 218 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 219 ; CHECK: ret 220 %cmp = icmp ugt i16 %a, %b 221 %ret = zext i1 %cmp to i16 222 ret i16 %ret 223 } 224 225 define i16 @icmp_uge_i16(i16 %a, i16 %b) { 226 ; CHECK: setp.ge.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 227 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 228 ; CHECK: ret 229 %cmp = icmp uge i16 %a, %b 230 %ret = zext i1 %cmp to i16 231 ret i16 %ret 232 } 233 234 define i16 @icmp_ult_i16(i16 %a, i16 %b) { 235 ; CHECK: setp.lt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 236 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 237 ; CHECK: ret 238 %cmp = icmp ult i16 %a, %b 239 %ret = zext i1 %cmp to i16 240 ret i16 %ret 241 } 242 243 define i16 @icmp_ule_i16(i16 %a, i16 %b) { 244 ; CHECK: setp.le.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 245 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 246 ; CHECK: ret 247 %cmp = icmp ule i16 %a, %b 248 %ret = zext i1 %cmp to i16 249 ret i16 %ret 250 } 251 252 define i16 @icmp_sgt_i16(i16 %a, i16 %b) { 253 ; CHECK: setp.gt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 254 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 255 ; CHECK: ret 256 %cmp = icmp sgt i16 %a, %b 257 %ret = zext i1 %cmp to i16 258 ret i16 %ret 259 } 260 261 define i16 @icmp_sge_i16(i16 %a, i16 %b) { 262 ; CHECK: setp.ge.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 263 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 264 ; CHECK: ret 265 %cmp = icmp sge i16 %a, %b 266 %ret = zext i1 %cmp to i16 267 ret i16 %ret 268 } 269 270 define i16 @icmp_slt_i16(i16 %a, i16 %b) { 271 ; CHECK: setp.lt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 272 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 273 ; CHECK: ret 274 %cmp = icmp slt i16 %a, %b 275 %ret = zext i1 %cmp to i16 276 ret i16 %ret 277 } 278 279 define i16 @icmp_sle_i16(i16 %a, i16 %b) { 280 ; CHECK: setp.le.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 281 ; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]] 282 ; CHECK: ret 283 %cmp = icmp sle i16 %a, %b 284 %ret = zext i1 %cmp to i16 285 ret i16 %ret 286 } 287 288 289 ;;; i8 290 291 define i8 @icmp_eq_i8(i8 %a, i8 %b) { 292 ; Comparison happens in 16-bit 293 ; CHECK: setp.eq.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 294 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 295 ; CHECK: ret 296 %cmp = icmp eq i8 %a, %b 297 %ret = zext i1 %cmp to i8 298 ret i8 %ret 299 } 300 301 define i8 @icmp_ne_i8(i8 %a, i8 %b) { 302 ; Comparison happens in 16-bit 303 ; CHECK: setp.ne.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 304 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 305 ; CHECK: ret 306 %cmp = icmp ne i8 %a, %b 307 %ret = zext i1 %cmp to i8 308 ret i8 %ret 309 } 310 311 define i8 @icmp_ugt_i8(i8 %a, i8 %b) { 312 ; Comparison happens in 16-bit 313 ; CHECK: setp.gt.u16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 314 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 315 ; CHECK: ret 316 %cmp = icmp ugt i8 %a, %b 317 %ret = zext i1 %cmp to i8 318 ret i8 %ret 319 } 320 321 define i8 @icmp_uge_i8(i8 %a, i8 %b) { 322 ; Comparison happens in 16-bit 323 ; CHECK: setp.ge.u16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 324 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 325 ; CHECK: ret 326 %cmp = icmp uge i8 %a, %b 327 %ret = zext i1 %cmp to i8 328 ret i8 %ret 329 } 330 331 define i8 @icmp_ult_i8(i8 %a, i8 %b) { 332 ; Comparison happens in 16-bit 333 ; CHECK: setp.lt.u16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 334 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 335 ; CHECK: ret 336 %cmp = icmp ult i8 %a, %b 337 %ret = zext i1 %cmp to i8 338 ret i8 %ret 339 } 340 341 define i8 @icmp_ule_i8(i8 %a, i8 %b) { 342 ; Comparison happens in 16-bit 343 ; CHECK: setp.le.u16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 344 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 345 ; CHECK: ret 346 %cmp = icmp ule i8 %a, %b 347 %ret = zext i1 %cmp to i8 348 ret i8 %ret 349 } 350 351 define i8 @icmp_sgt_i8(i8 %a, i8 %b) { 352 ; Comparison happens in 16-bit 353 ; CHECK: setp.gt.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 354 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 355 ; CHECK: ret 356 %cmp = icmp sgt i8 %a, %b 357 %ret = zext i1 %cmp to i8 358 ret i8 %ret 359 } 360 361 define i8 @icmp_sge_i8(i8 %a, i8 %b) { 362 ; Comparison happens in 16-bit 363 ; CHECK: setp.ge.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 364 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 365 ; CHECK: ret 366 %cmp = icmp sge i8 %a, %b 367 %ret = zext i1 %cmp to i8 368 ret i8 %ret 369 } 370 371 define i8 @icmp_slt_i8(i8 %a, i8 %b) { 372 ; Comparison happens in 16-bit 373 ; CHECK: setp.lt.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 374 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 375 ; CHECK: ret 376 %cmp = icmp slt i8 %a, %b 377 %ret = zext i1 %cmp to i8 378 ret i8 %ret 379 } 380 381 define i8 @icmp_sle_i8(i8 %a, i8 %b) { 382 ; Comparison happens in 16-bit 383 ; CHECK: setp.le.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}} 384 ; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]] 385 ; CHECK: ret 386 %cmp = icmp sle i8 %a, %b 387 %ret = zext i1 %cmp to i8 388 ret i8 %ret 389 } 390
