1 ; RUN: llc -march=x86-64 -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-bottomup -verify-machineinstrs < %s 2 ; RUN: llc -march=x86-64 -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-topdown -verify-machineinstrs < %s 3 ; REQUIRES: asserts 4 ; XFAIL: cygwin,mingw32 5 ; 6 ; Test the LiveIntervals::handleMove() function. 7 ; 8 ; Moving the DIV32r instruction exercises the regunit update code because 9 ; %EDX has a live range into the function and is used by the DIV32r. 10 ; 11 ; Here sinking a kill + dead def: 12 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def>, %EDX<imp-def,dead>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use> 13 ; %vreg4: [48r,144r:0) 0@48r 14 ; --> [48r,180r:0) 0@48r 15 ; DH: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0@0B-phi 1@144r 2@128r 16 ; --> [0B,16r:0)[128r,180r:2)[180r,180d:1) 0@0B-phi 1@180r 2@128r 17 ; DL: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0@0B-phi 1@144r 2@128r 18 ; --> [0B,16r:0)[128r,180r:2)[180r,180d:1) 0@0B-phi 1@180r 2@128r 19 ; 20 define i32 @f1(i32 %a, i32 %b, i32 %c) nounwind uwtable readnone ssp { 21 entry: 22 %y = add i32 %c, 1 23 %x = udiv i32 %b, %a 24 %add = add nsw i32 %y, %x 25 ret i32 %add 26 } 27 28 ; Same as above, but moving a kill + live def: 29 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def,dead>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use> 30 ; %vreg4: [48r,144r:0) 0@48r 31 ; --> [48r,180r:0) 0@48r 32 ; DH: [0B,16r:0)[128r,144r:2)[144r,184r:1) 0@0B-phi 1@144r 2@128r 33 ; --> [0B,16r:0)[128r,180r:2)[180r,184r:1) 0@0B-phi 1@180r 2@128r 34 ; DL: [0B,16r:0)[128r,144r:2)[144r,184r:1) 0@0B-phi 1@144r 2@128r 35 ; --> [0B,16r:0)[128r,180r:2)[180r,184r:1) 0@0B-phi 1@180r 2@128r 36 ; 37 define i32 @f2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp { 38 entry: 39 %y = sub i32 %c, %d 40 %x = urem i32 %b, %a 41 %add = add nsw i32 %x, %y 42 ret i32 %add 43 } 44 45 ; Moving a use below the existing kill (%vreg5): 46 ; Moving a tied virtual register def (%vreg11): 47 ; 48 ; 96B -> 120B: %vreg11<def,tied1> = SUB32rr %vreg11<tied0>, %vreg5 49 ; %vreg11: [80r,96r:1)[96r,144r:0) 0@96r 1@80r 50 ; --> [80r,120r:1)[120r,144r:0) 0@120r 1@80r 51 ; %vreg5: [16r,112r:0) 0@16r 52 ; --> [16r,120r:0) 0@16r 53 ; 54 define i32 @f3(i32 %a, i32 %b) nounwind uwtable readnone ssp { 55 entry: 56 %y = sub i32 %a, %b 57 %x = add i32 %a, %b 58 %r = mul i32 %x, %y 59 ret i32 %r 60 } 61 62 ; Move EFLAGS dead def across another def: 63 ; handleMove 208B -> 36B: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead> 64 ; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@208r 1@224r 2@272r 3@160r 4@20r 5@304r 65 ; --> [20r,20d:4)[36r,36d:0)[160r,160d:3)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@36r 1@224r 2@272r 3@160r 4@20r 5@304r 66 ; 67 define i32 @f4(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp { 68 entry: 69 %x = sub i32 %a, %b 70 %y = sub i32 %b, %c 71 %z = sub i32 %c, %d 72 %r1 = udiv i32 %x, %y 73 %r2 = mul i32 %z, %r1 74 ret i32 %r2 75 } 76
