Home | History | Annotate | Download | only in TableGen 
      1 // RUN: llvm-tblgen %s | FileCheck %s
      2 
      3 class XD { bits<4> Prefix = 11; }
      4 // CHECK: Prefix = { 1, 1, 0, 0 };
      5 class XS { bits<4> Prefix = 12; }
      6 class VEX { bit hasVEX_4VPrefix = 1; }
      7 
      8 def xd : XD;
      9 
     10 class BaseI {
     11   bits<4> Prefix = 0;
     12   bit hasVEX_4VPrefix = 0;
     13 }
     14 
     15 class I<bits<4> op> : BaseI {
     16   bits<4> opcode = op;
     17   int val = !if(!eq(Prefix, xd.Prefix), 7, 21);
     18   int check = !if(hasVEX_4VPrefix, 0, 10);
     19 }
     20 
     21 multiclass R {
     22   def rr : I<4>;
     23 }
     24 
     25 multiclass M {
     26   def rm : I<2>;
     27 }
     28 
     29 multiclass Y {
     30   defm SS : R, M, XD;
     31 // CHECK: Prefix = { 1, 1, 0, 0 };
     32 // CHECK: Prefix = { 1, 1, 0, 0 };
     33   defm SD : R, M, XS;
     34 }
     35 
     36 // CHECK: int check = 0;
     37 defm Instr : Y, VEX;
     38 
     39 
     40 // Anonymous defm.
     41 
     42 multiclass SomeAnonymous<int x> {
     43   def rm;
     44   def mr;
     45 }
     46 
     47 // These multiclasses shouldn't conflict.
     48 defm : SomeAnonymous<1>;
     49 defm : SomeAnonymous<2>;