Home | History | Annotate | Download | only in arch 
      1 /****************************************************************************
      2  ****************************************************************************
      3  ***
      4  ***   This header was automatically generated from a Linux kernel header
      5  ***   of the same name, to make information necessary for userspace to
      6  ***   call into the kernel available to libc.  It contains only constants,
      7  ***   structures, and macros generated from the original header, and thus,
      8  ***   contains no copyrightable information.
      9  ***
     10  ****************************************************************************
     11  ****************************************************************************/
     12 #ifndef __ASM_ARCH_OMAP_FPGA_H
     13 #define __ASM_ARCH_OMAP_FPGA_H
     14 
     15 #define omap1510_fpga_init_irq() (0)
     16 
     17 #define fpga_read(reg) __raw_readb(reg)
     18 #define fpga_write(val, reg) __raw_writeb(val, reg)
     19 
     20 #define H2P2_DBG_FPGA_BASE 0xE8000000
     21 #define H2P2_DBG_FPGA_SIZE SZ_4K
     22 #define H2P2_DBG_FPGA_START 0x04000000
     23 
     24 #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
     25 #define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10)
     26 #define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12)
     27 #define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14)
     28 #define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16)
     29 #define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18)
     30 #define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A)
     31 #define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C)
     32 
     33 struct h2p2_dbg_fpga {
     34 
     35  u16 smc91x[8];
     36 
     37  u16 fpga_rev;
     38  u16 board_rev;
     39  u16 gpio_outputs;
     40  u16 leds;
     41 
     42  u16 misc_inputs;
     43  u16 lan_status;
     44  u16 lan_reset;
     45  u16 reserved0;
     46 
     47  u16 ps2_data;
     48  u16 ps2_ctrl;
     49 
     50 };
     51 
     52 #define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
     53 #define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
     54 #define H2P2_DBG_FPGA_LED_RED (1 << 13)
     55 #define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
     56 
     57 #define H2P2_DBG_FPGA_LOAD_METER (1 << 0)
     58 #define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
     59 #define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
     60 
     61 #define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
     62 #define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
     63 
     64 #define OMAP1510_FPGA_BASE 0xE8000000
     65 #define OMAP1510_FPGA_SIZE SZ_4K
     66 #define OMAP1510_FPGA_START 0x08000000
     67 
     68 #define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
     69 #define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
     70 
     71 #define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
     72 #define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
     73 #define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
     74 #define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
     75 
     76 #define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
     77 #define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
     78 
     79 #define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
     80 #define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
     81 
     82 #define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
     83 #define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
     84 
     85 #define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
     86 #define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
     87 #define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
     88 #define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
     89 #define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
     90 #define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
     91 #define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
     92 #define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
     93 #define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
     94 #define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
     95 
     96 #define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
     97 
     98 #define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
     99 #define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
    100 #define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
    101 #define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
    102 #define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
    103 #define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
    104 #define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
    105 #define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
    106 #define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
    107 #define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
    108 #define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
    109 
    110 #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
    111 
    112 #define OMAP1510_FPGA_RESET_VALUE 0x42
    113 
    114 #define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
    115 #define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
    116 #define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
    117 #define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
    118 #define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
    119 #define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
    120 #define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
    121 #define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
    122 
    123 #define OMAP1510_FPGA_HID_SCLK (1<<0)
    124 #define OMAP1510_FPGA_HID_MOSI (1<<1)
    125 #define OMAP1510_FPGA_HID_nSS (1<<2)
    126 #define OMAP1510_FPGA_HID_nHSUS (1<<3)
    127 #define OMAP1510_FPGA_HID_MISO (1<<4)
    128 #define OMAP1510_FPGA_HID_ATN (1<<5)
    129 #define OMAP1510_FPGA_HID_rsrvd (1<<6)
    130 #define OMAP1510_FPGA_HID_RESETn (1<<7)
    131 
    132 #define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
    133 
    134 #define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE
    135 #define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0)
    136 #define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1)
    137 #define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2)
    138 #define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3)
    139 #define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4)
    140 #define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5)
    141 #define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6)
    142 #define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7)
    143 #define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8)
    144 #define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9)
    145 #define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10)
    146 #define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11)
    147 #define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12)
    148 #define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13)
    149 #define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14)
    150 #define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15)
    151 #define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16)
    152 #define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17)
    153 #define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18)
    154 #define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19)
    155 #define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20)
    156 #define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21)
    157 #define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22)
    158 #define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23)
    159 
    160 #endif
    161