Lines Matching defs:AN
10 // This file defines an instruction selector for the AArch64 target.
72 /// the fields match. This operand's job is simply to add an
121 // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
122 // is between 1 and 32 for a destination w-register, or 1 and 64 for an
131 // could have 2^64 as an actual operand. Need 65 bits of precision.
155 // hunting for a base and an offset if we want. Of course, since
157 // probably restricted to the load/store pair's simm7 as an offset
366 AtomicSDNode *AN = cast<AtomicSDNode>(Node);
367 EVT VT = AN->getMemoryVT();
382 for (unsigned i = 1; i < AN->getNumOperands(); ++i)
383 Ops.push_back(AN->getOperand(i));
385 Ops.push_back(CurDAG->getTargetConstant(AN->getOrdering(), MVT::i32));
386 Ops.push_back(AN->getOperand(0)); // Chain moves to the end
389 AN->getValueType(0), MVT::Other,
494 // XZR and WZR are probably even better than an actual move: most of the
