Lines Matching defs:CC
647 // b.cc IfTrue
867 CCAssignFn *AArch64TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
869 switch(CC) {
1595 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1596 switch (CC) {
1623 ISD::CondCode CC, SDValue &A64cc,
1632 if (isSignedIntSetCC(CC)) {
1644 switch (CC) {
1649 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1656 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1663 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1670 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1678 A64CC::CondCodes CondCode = IntCCToA64CC(CC);
1681 DAG.getCondCode(CC));
1684 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
1689 switch (CC) {
1772 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1779 // LHS, RHS and CC appropriately for the rest of this function to continue.
1780 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
1786 CC = ISD::SETNE;
1795 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
1805 CondCode = FPCCToA64CC(CC, Alternative);
1808 DAG.getCondCode(CC));
2220 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2225 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2231 CC = ISD::SETNE;
2240 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2250 CondCode = FPCCToA64CC(CC, Alternative);
2253 DAG.getCondCode(CC));
2294 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2304 if (CC == ISD::SETNE) {
2321 !isUnsignedIntSetCC(CC)) {
2325 CC = getSetCCSwappedOperands(CC);
2332 if (ISD::SETNE == CC) {
2334 CC = ISD::SETEQ;
2345 switch (CC) {
2356 CC = ISD::SETEQ;
2363 CC = getSetCCSwappedOperands(CC);
2376 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2391 CC = getSetCCSwappedOperands(CC);
2407 // Some register compares have to be implemented with swapped CC and operands,
2414 switch (CC) {
2422 CC = ISD::SETEQ;
2426 CC = ISD::SETLT;
2431 CC = ISD::SETGT;
2435 CC = ISD::SETLE;
2440 CC = ISD::SETGE;
2444 CC = ISD::SETLT;
2449 CC = ISD::SETGT;
2453 CC = ISD::SETLE;
2458 CC = ISD::SETGE;
2466 CC = ISD::SETLT;
2475 CC = ISD::SETLT;
2481 CC = getSetCCSwappedOperands(CC);
2486 SDValue NeonCmp = DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2503 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2512 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2527 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2538 CondCode = FPCCToA64CC(CC, Alternative);
2541 DAG.getCondCode(CC));
