Lines Matching full:arm
1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
17 #include "ARM.h"
227 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
228 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
233 unsigned SReg = Reg - ARM::S0;
254 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
255 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
260 unsigned QReg = Reg - ARM::Q0;
335 if(ARM::GPRPairRegClass.contains(Reg)) {
338 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
441 if (!ARM::DPRRegClass.contains(*SR))
443 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
468 if (ARM::GPRPairRegClass.contains(RegBegin)) {
470 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
472 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
502 if (RC == ARM::GPRPairRegClassID) {
510 ARM::gsub_0 : ARM::gsub_1);
532 if (!ARM::QPRRegClass.contains(Reg))
536 ARM::dsub_0 : ARM::dsub_1);
551 if(!ARM::GPRPairRegClass.contains(Reg))
553 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
597 // the way symbol offsets are encoded with the current Darwin ARM
645 // Emit ARM Build Attributes
719 // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default.
728 // to appear in the .ARM.attributes section in ELF.
1001 if (Opcode == ARM::BR_JTadd)
1003 else if (Opcode == ARM::BR_JTm)
1051 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1064 if (MI->getOpcode() == ARM::t2TBB_JT) {
1068 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1080 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
1122 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1128 SrcReg = DstReg = ARM::SP;
1137 assert(DstReg == ARM::SP &&
1150 case ARM::tPUSH:
1153 case ARM::STMDB_UPD:
1154 case ARM::t2STMDB_UPD:
1155 case ARM::VSTMDDB_UPD:
1156 assert(SrcReg == ARM::SP &&
1168 case ARM::STR_PRE_IMM:
1169 case ARM::STR_PRE_REG:
1170 case ARM::t2STR_PRE:
1171 assert(MI->getOperand(2).getReg() == ARM::SP &&
1176 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1179 if (SrcReg == ARM::SP) {
1185 case ARM::MOVr:
1186 case ARM::tMOVr:
1189 case ARM::ADDri:
1192 case ARM::SUBri:
1193 case ARM::t2SUBri:
1196 case ARM::tSUBspi:
1199 case ARM::tADDspi:
1200 case ARM::tADDrSPi:
1203 case ARM::tLDRpci: {
1221 if (DstReg == FramePtr && FramePtr != ARM::SP)
1224 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1225 else if (DstReg == ARM::SP) {
1233 } else if (DstReg == ARM::SP) {
1253 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1272 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1273 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1274 case ARM::LEApcrel:
1275 case ARM::tLEApcrel:
1276 case ARM::t2LEApcrel: {
1280 ARM::t2LEApcrel ? ARM::t2ADR
1281 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1282 : ARM::ADR))
1290 case ARM::LEApcrelJT:
1291 case ARM::tLEApcrelJT:
1292 case ARM::t2LEApcrelJT: {
1297 ARM::t2LEApcrelJT ? ARM::t2ADR
1298 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1299 : ARM::ADR))
1309 case ARM::BX_CALL: {
1310 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1311 .addReg(ARM::LR)
1312 .addReg(ARM::PC)
1319 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1323 case ARM::tBX_CALL: {
1324 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1325 .addReg(ARM::LR)
1326 .addReg(ARM::PC)
1331 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1338 case ARM::BMOVPCRX_CALL: {
1339 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1340 .addReg(ARM::LR)
1341 .addReg(ARM::PC)
1348 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1349 .addReg(ARM::PC)
1358 case ARM::BMOVPCB_CALL: {
1359 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1360 .addReg(ARM::LR)
1361 .addReg(ARM::PC)
1371 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1378 case ARM::MOVi16_ga_pcrel:
1379 case ARM::t2MOVi16_ga_pcrel: {
1381 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1394 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1414 case ARM::MOVTi16_ga_pcrel:
1415 case ARM::t2MOVTi16_ga_pcrel: {
1417 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1418 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1432 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1451 case ARM::tPICADD: {
1463 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1466 .addReg(ARM::PC)
1472 case ARM::PICADD: {
1484 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1486 .addReg(ARM::PC)
1495 case ARM::PICSTR:
1496 case ARM::PICSTRB:
1497 case ARM::PICSTRH:
1498 case ARM::PICLDR:
1499 case ARM::PICLDRB:
1500 case ARM::PICLDRH:
1501 case ARM::PICLDRSB:
1502 case ARM::PICLDRSH: {
1519 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1520 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1521 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1522 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1523 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1524 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1525 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1526 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1530 .addReg(ARM::PC)
1539 case ARM::CONSTPOOL_ENTRY: {
1563 case ARM::t2BR_JT: {
1565 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1566 .addReg(ARM::PC)
1576 case ARM::t2TBB_JT: {
1578 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1579 .addReg(ARM::PC)
1591 case ARM::t2TBH_JT: {
1593 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1594 .addReg(ARM::PC)
1604 case ARM::tBR_JTr:
1605 case ARM::BR_JTr: {
1609 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1610 ARM::MOVr : ARM::tMOVr;
1612 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1618 if (Opc == ARM::MOVr)
1623 if (Opc == ARM::tMOVr)
1630 case ARM::BR_JTm: {
1636 TmpInst.setOpcode(ARM::LDRi12);
1637 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1641 TmpInst.setOpcode(ARM::LDRrs);
1642 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1656 case ARM::BR_JTadd: {
1659 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1660 .addReg(ARM::PC)
1673 case ARM::TRAP: {
1685 case ARM::TRAPNaCl: {
1692 case ARM::tTRAP: {
1704 case ARM::t2Int_eh_sjlj_setjmp:
1705 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1706 case ARM::tInt_eh_sjlj_setjmp: {
1719 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1721 .addReg(ARM::PC)
1726 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1729 .addReg(ARM::CPSR)
1736 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1746 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1747 .addReg(ARM::R0)
1748 .addReg(ARM::CPSR)
1755 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1761 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1762 .addReg(ARM::R0)
1763 .addReg(ARM::CPSR)
1773 case ARM::Int_eh_sjlj_setjmp_nofp:
1774 case ARM::Int_eh_sjlj_setjmp: {
1785 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1787 .addReg(ARM::PC)
1795 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1803 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1804 .addReg(ARM::R0)
1812 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1813 .addReg(ARM::PC)
1814 .addReg(ARM::PC)
1823 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1824 .addReg(ARM::R0)
1833 case ARM::Int_eh_sjlj_longjmp: {
1840 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1841 .addReg(ARM::SP)
1848 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1856 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1857 .addReg(ARM::R7)
1864 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1871 case ARM::tInt_eh_sjlj_longjmp: {
1879 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1889 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1890 .addReg(ARM::SP)
1896 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1904 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1905 .addReg(ARM::R7)
1912 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
