Lines Matching full:arm
1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
15 #include "ARM.h"
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
49 BasePtr(ARM::R6) {
107 Reserved.set(ARM::SP);
108 Reserved.set(ARM::PC);
109 Reserved.set(ARM::FPSCR);
110 Reserved.set(ARM::APSR_NZCV);
117 Reserved.set(ARM::R9);
120 assert(ARM::D31 == ARM::D16 + 15);
122 Reserved.set(ARM::D16 + i);
124 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
139 case ARM::GPRRegClassID:
140 case ARM::SPRRegClassID:
141 case ARM::DPRRegClassID:
142 case ARM::QPRRegClassID:
143 case ARM::QQPRRegClassID:
144 case ARM::QQQQPRRegClassID:
145 case ARM::GPRPairRegClassID:
156 return &ARM::GPRRegClass;
161 if (RC == &ARM::CCRRegClass)
174 case ARM::tGPRRegClassID:
176 case ARM::GPRRegClassID: {
180 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
181 case ARM::DPRRegClassID:
189 if (ARM::GPRPairRegClass.contains(*Supers))
190 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
272 case ARM::DPRRegClassID:
273 case ARM::DPR_8RegClassID:
274 case ARM::DPR_VFP2RegClassID:
275 case ARM::QPRRegClassID:
276 case ARM::QPR_8RegClassID:
277 case ARM::QPR_VFP2RegClassID:
278 case ARM::SPRRegClassID:
279 case ARM::SPR_8RegClassID:
371 return ARM::SP;
398 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
496 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
497 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
498 case ARM::t2LDRi12: case ARM::t2LDRi8:
499 case ARM::t2STRi12: case ARM::t2STRi8:
500 case ARM::VLDRS: case ARM::VLDRD:
501 case ARM::VSTRS: case ARM::VSTRD:
502 case ARM::tSTRspi: case ARM::tLDRspi:
523 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
566 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
567 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
596 int Off = Offset; // ARM doesn't need the general 64-bit offsets
709 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
749 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
