Lines Matching full:arm
1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
16 #include "ARM.h"
246 if (MO.getReg() == ARM::CPSR)
277 // Are we NEON in ARM mode and have a predicate operand? If so, I know
283 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
497 TII.get(ARM::VMOVSR), MoveReg)
507 TII.get(ARM::VMOVRS), MoveReg)
526 Opc = ARM::FCONSTD;
529 Opc = ARM::FCONSTS;
549 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
568 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
569 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
570 &ARM::GPRRegClass;
584 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
609 TII.get(ARM::t2LDRpci), DestReg)
614 TII.get(ARM::LDRcp), DestReg)
628 (const TargetRegisterClass*)&ARM::rGPRRegClass :
629 (const TargetRegisterClass*)&ARM::GPRRegClass;
646 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
649 Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
652 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
680 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
688 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
695 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
713 TII.get(ARM::t2LDRi12), NewDestReg)
717 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
762 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
922 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
938 (const TargetRegisterClass*)&ARM::tGPRRegClass :
939 (const TargetRegisterClass*)&ARM::GPRRegClass;
941 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
980 // ARM halfword load/stores and signed byte loads need an additional
994 // ARM halfword load/stores and signed byte loads need an additional
1020 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1022 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1025 Opc = ARM::LDRBi12;
1027 Opc = ARM::LDRSB;
1031 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1039 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1041 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1043 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1046 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1054 Opc = ARM::t2LDRi8;
1056 Opc = ARM::t2LDRi12;
1058 Opc = ARM::LDRi12;
1060 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1068 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1069 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1071 Opc = ARM::VLDRS;
1082 Opc = ARM::VLDRD;
1102 TII.get(ARM::VMOVSR), MoveReg)
1139 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1140 (const TargetRegisterClass*)&ARM::GPRRegClass);
1141 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1150 StrOpc = ARM::t2STRBi8;
1152 StrOpc = ARM::t2STRBi12;
1154 StrOpc = ARM::STRBi12;
1163 StrOpc = ARM::t2STRHi8;
1165 StrOpc = ARM::t2STRHi12;
1167 StrOpc = ARM::STRH;
1177 StrOpc = ARM::t2STRi8;
1179 StrOpc = ARM::t2STRi12;
1181 StrOpc = ARM::STRi12;
1190 TII.get(ARM::VMOVRS), MoveReg)
1194 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1196 StrOpc = ARM::VSTRS;
1206 StrOpc = ARM::VSTRD;
1323 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1325 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1334 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1346 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1348 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1372 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1382 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1384 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1394 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1452 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1456 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1466 CmpOpc = ARM::t2CMPrr;
1468 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1471 CmpOpc = ARM::CMPrr;
1473 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1516 TII.get(ARM::FMSTAT)));
1535 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1537 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1538 (const TargetRegisterClass*)&ARM::GPRRegClass;
1545 .addImm(ARMPred).addReg(ARM::CPSR);
1562 unsigned Result = createResultReg(&ARM::DPRRegClass);
1564 TII.get(ARM::VCVTDS), Result)
1581 unsigned Result = createResultReg(&ARM::SPRRegClass);
1583 TII.get(ARM::VCVTSD), Result)
1622 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1623 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1648 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1649 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1701 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1708 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1709 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1711 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1713 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1715 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1720 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1723 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1790 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1793 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1796 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1808 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1835 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1838 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1841 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
2023 TII.get(ARM::VMOVRRD), VA.getLocReg())
2033 Addr.Base.Reg = ARM::SP;
2067 TII.get(ARM::VMOVDRR), ResultReg)
2148 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2171 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2182 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2184 return isThumb2 ? ARM::tBL : ARM::BL;
2204 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2413 // ARM calls don't take a predicate, but tBL / tBLX do.
2500 LdrOpc = ARM::t2LDRi12;
2501 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2503 LdrOpc = ARM::LDRi12;
2504 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2579 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2618 // ARM Thumb
2627 // - For ARM can never be PC.
2632 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2633 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2644 { // ARM Opc S Shift Imm
2645 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2646 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2647 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2648 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2649 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2650 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2653 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2654 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2655 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2656 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2657 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2658 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2662 { // ARM Opc S Shift Imm
2663 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2664 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2665 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2666 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2667 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2668 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2671 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2672 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2673 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2674 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2675 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2676 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2698 assert(ARM::KILL != Opc && "Invalid table entry");
2701 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2706 bool setsCPSR = &ARM::tGPRRegClass == RC;
2707 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2733 MIB.addReg(ARM::CPSR, RegState::Define);
2745 // On ARM, in general, integer casts don't involve legal types; this code
2781 unsigned Opc = ARM::MOVsr;
2792 Opc = ARM::MOVsi;
2800 if (Opc == ARM::MOVsr) {
2805 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2812 if (Opc == ARM::MOVsi)
2814 else if (Opc == ARM::MOVsr) {
2901 uint16_t Opc[2]; // ARM, Thumb.
2906 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2907 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2908 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2909 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2910 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2969 TII.get(ARM::t2LDRpci), DestReg1)
2971 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2975 DL, TII.get(ARM::LDRcp), DestReg1)
2977 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
3049 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3071 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3076 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
