Lines Matching full:arm
1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
33 cl::desc("Align ARM NEON spills in prolog and epilog"));
67 // stack frame. ARM (especially Thumb) has small immediate offset to
96 if (MI->getOpcode() == ARM::LDMIA_RET ||
97 MI->getOpcode() == ARM::t2LDMIA_RET ||
98 MI->getOpcode() == ARM::LDMIA_UPD ||
99 MI->getOpcode() == ARM::t2LDMIA_UPD ||
100 MI->getOpcode() == ARM::VLDMDIA_UPD) {
108 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
109 MI->getOpcode() == ARM::LDR_POST_REG ||
110 MI->getOpcode() == ARM::t2LDR_POST) &&
112 MI->getOperand(1).getReg() == ARM::SP)
125 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
128 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
178 case ARM::R4:
179 case ARM::R5:
180 case ARM::R6:
181 case ARM::R7:
182 case ARM::LR:
188 case ARM::R8:
189 case ARM::R9:
190 case ARM::R10:
191 case ARM::R11:
204 if (Reg == ARM::D8)
206 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) {
223 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
250 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
270 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
299 TII.get(ARM::BICri), ARM::SP)
300 .addReg(ARM::SP, RegState::Kill)
309 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
310 .addReg(ARM::SP, RegState::Kill));
312 TII.get(ARM::t2BICri), ARM::R4)
313 .addReg(ARM::R4, RegState::Kill)
315 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
316 .addReg(ARM::R4, RegState::Kill));
330 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
331 .addReg(ARM::SP)
334 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
336 .addReg(ARM::SP));
396 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
406 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
408 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
410 ARM::tMOVr),
411 ARM::SP)
412 .addReg(ARM::R4));
415 // Thumb2 or ARM.
417 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
420 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
421 ARM::SP)
432 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
439 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
445 if (RetOpcode == ARM::TCRETURNdi) {
447 (STI.isTargetIOS() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
448 ARM::TAILJMPd;
461 } else if (RetOpcode == ARM::TCRETURNri) {
463 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
502 FrameReg = ARM::SP;
601 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
609 if (Reg == ARM::LR) {
631 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
632 .addReg(ARM::SP).setMIFlags(MIFlags));
637 ARM::SP)
639 .addReg(ARM::SP).setMIFlags(MIFlags)
659 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
660 RetOpcode == ARM::TCRETURNri);
672 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
675 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {
676 Reg = ARM::PC;
677 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
696 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
697 .addReg(ARM::SP));
708 if (Regs[0] == ARM::PC)
709 Regs[0] = ARM::LR;
712 .addReg(ARM::SP, RegState::Define)
713 .addReg(ARM::SP);
714 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
716 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
745 unsigned DNum = CSI[i].getReg() - ARM::D8;
776 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
777 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
778 .addReg(ARM::SP)
782 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
784 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
785 .addReg(ARM::R4, RegState::Kill)
792 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
793 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
794 .addReg(ARM::R4);
801 unsigned NextReg = ARM::D8;
806 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
807 &ARM::QQPRRegClass);
809 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
810 ARM::R4)
811 .addReg(ARM::R4, RegState::Kill).addImm(16)
824 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
825 &ARM::QQPRRegClass);
827 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
828 .addReg(ARM::R4).addImm(16).addReg(NextReg)
836 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
837 &ARM::QPRRegClass);
839 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
840 .addReg(ARM::R4).addImm(16).addReg(SupReg));
849 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
851 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
855 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
880 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
902 if (CSI[i].getReg() == ARM::D8) {
915 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
916 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
920 unsigned NextReg = ARM::D8;
924 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
925 &ARM::QQPRRegClass);
926 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
927 .addReg(ARM::R4, RegState::Define)
928 .addReg(ARM::R4, RegState::Kill).addImm(16)
940 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
941 &ARM::QQPRRegClass);
942 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
943 .addReg(ARM::R4).addImm(16)
951 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
952 &ARM::QPRRegClass);
953 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
954 .addReg(ARM::R4).addImm(16));
961 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
962 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
965 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
978 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
980 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
981 unsigned FltOpc = ARM::VSTMDDB_UPD;
1016 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1017 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1018 unsigned FltOpc = ARM::VLDMDIA_UPD;
1059 if (I->getOpcode() == ARM::ADDri) {
1132 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills))
1143 MF.getRegInfo().setPhysRegUsed(ARM::R4);
1175 MRI.setPhysRegUsed(ARM::R4);
1180 MRI.setPhysRegUsed(ARM::LR);
1190 MRI.setPhysRegUsed(ARM::R4);
1211 if (!ARM::GPRRegClass.contains(Reg))
1218 if (Reg == ARM::LR)
1226 case ARM::LR:
1229 case ARM::R4: case ARM::R5:
1230 case ARM::R6: case ARM::R7:
1243 case ARM::R4: case ARM::R5:
1244 case ARM::R6: case ARM::R7:
1245 case ARM::LR:
1296 MRI.setPhysRegUsed(ARM::LR);
1299 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1319 isARMLowRegister(Reg) || Reg == ARM::LR) {
1349 Reg == ARM::LR)) {
1372 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1381 MRI.setPhysRegUsed(ARM::LR);
1416 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1424 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
